LMK04228
- JEDEC JESD204B Support
- Ultra-Low RMS
Jitter
- 156 fs RMS Jitter (12 kHz to 20 MHz)
- 245 fs RMS Jitter (100 Hz to 20 MHz)
- –162.5 dBc/Hz Noise Floor at 245.76 MHz
- Up to 14 Differential Device Clocks from
PLL2
- Up to 7 SYSREF Clocks
- Maximum Clock Output Frequency: 1.25 GHz
- LVPECL, LVDS Programmable Outputs From PLL2
- Buffered VCXO or Crystal Output From
PLL1
- LVPECL, LVDS, 2xLVCMOS Programmable
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- Up to 3 Redundant Input
Clocks
- Automatic and Manual Switch-Over Modes
- Hitless Switching and LOS
- Integrated Low-Noise Crystal Oscillator Circuit
- Holdover Mode When Input Clocks are Lost
- Up to 3 Redundant Input
Clocks
- PLL2
- Normalized [1 Hz] PLL Noise Floor of
–224 dBc/Hz - Phase Detector Rate up to 155 MHz
- OSCin Frequency-Doubler
- Two Integrated Low-Noise VCOs
- Normalized [1 Hz] PLL Noise Floor of
- 50% Duty Cycle Output Divides, 1 to 32
(Even and Odd) - Precision Digital Delay
- 25-ps Step Analog Delay
- Multi-Mode: Dual PLL or Single PLL
- Industrial Temperature Range: –40°C to 85°C
- 3.15-V to 3.45-V Operation
- Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
The LMK04228 device is the industry’s high performance clock conditioner with JEDEC JESD204B support.
The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high performance outputs for traditional clocking systems.
The high performance combined with features like the ability to trade off between power or performance, dual VCOs, holdover, and per-output adjustable analog and digital delay make the LMK04228 ideal for providing flexible high performance clocking trees.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK04228 Ultra-Low Noise, JESD204B-Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. A) | PDF | HTML | 2019/7/23 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
CODELOADER — CodeLoader Device Register Programming v4.19.0
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
CLOCKDESIGNTOOL — Clock Design Tool Software
時脈設計工具軟體可協助進行零件選擇、迴路濾波器設計，以及計時裝置解決方案模擬。當您輸入所需的輸出頻率和參考頻率 (選用) 時，此工具可提供符合指定需求、分頻器值和建議迴路濾波器的 TI 裝置，以將抖動降到最低。
CLOCKDESIGNTOOL 教學影片
我應該使用哪個軟體？
產品 | 迴路濾波器和裝置配置 + 模擬 | 模擬工具 | 裝置暫存器程式化 |
LMX24xx PLL 系列 | EasyPLL | ||
LMX25xx PLL+VCO 系列 | 時脈設計工具 | ||
LMK 抖動清除器及分配器 |
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (NKD) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。