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LMX1906-SP

現行

具有 SYSREF 和 FPGA 時鐘的抗輻射保證 (RHA) 15GHz 緩衝器、倍頻器和分頻器

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產品規格表

LMX1906-SP

現行
產品規格表 立即訂購

產品詳細資料

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HTQFP (PAP) 64 144 mm² 12 x 12
  • SMD #5962-23202
    • Total ionizing dose 100krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 87MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 87MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, and 7
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature
  • SMD #5962-23202
    • Total ionizing dose 100krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 87MeV - cm2 /mg
    • Single event functional interrupt (SEFI) immune up to 87MeV - cm2 /mg
  • Clock buffer for 300MHz to 15GHz frequency
  • Ultra-Low Noise
    • Noise floor of –159dBc/Hz at 6GHz output
    • 36-fs additive jitter (100Hz to fCLK) at 6GHz output
    • 5fs additive jitter (100Hz - 100MHz)
  • 4 high-frequency clocks with corresponding SYSREF outputs
    • Shared divide by 1 (Buffer), 2, 3, 4, 5, and 7
    • Shared programmable multiplier x2, x3, and x4
  • Support pin mode options to configure the device without SPI
  • LOGICLK output with corresponding SYSREF output
    • On separate divide bank
    • 1, 2, 4 pre-divider
    • 1 (bypass), 2, …, 1023 post divider
  • 8 programmable output power levels
  • Synchronized SYSREF clock outputs
    • 508 delay step adjustments of less than 2.5ps each at 12.8GHz
    • Generator and repeater modes
    • Windowing feature for SYSREFREQ pins to optimize timing
  • SYNC feature to all divides and multiple devices
  • 2.5V operating voltage
  • –55ºC to 125ºC operating temperature

The LMX1906-SP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.

The LMX1906-SP is an buffer, divider and multiplier that features high frequency, ultra-low jitter, and SYSREF outputs. This device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. Each of the 4 high frequency clock outputs and additional LOGICLK output is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. This device can distribute the multichannel, low skew, ultra-low noise local oscillator signals to multiple mixers by disabling the SYSREF outputs.
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重要文件 類型 標題 格式選項 日期
* Data sheet LMX1906-SP Space Grade Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider datasheet (Rev. A) PDF | HTML 2025年 5月 20日
* Radiation & reliability report LMX1906-SP Total Ionizing Dose Report PDF | HTML 2024年 1月 5日
* Radiation & reliability report LMX1906-SP Single Event Effects Report 2023年 11月 15日
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 2025年 6月 17日
Application note Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025年 4月 11日
Certificate LMX1906EVM-CVAL EU Declaration of Conformity (DoC) 2023年 9月 14日

設計與開發

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開發板

LMX1906EVM-CVAL — LMX1906-SP 評估模組

LMX1906-SP 評估模組 (EVM) 設計旨在評估 LMX1906-SP 的性能，其為四路輸出、超低附加抖動無線電頻率 (RF) 緩衝器、分頻器和倍頻器。此裝置可緩衝高達 18GHz 的 RF 頻率，乘上最高 6.4GHz 的 RF 輸出，並將輸出除以最高 6.4GHz。可程式設計邏輯閘陣列 (FPGA) 和邏輯時鐘中隨附獨立的輔助時鐘分頻器，而每個輸出均包含具皮秒精度及延遲微調功能的系統參考 (SYSREF) 補數。多個裝置可針對廣泛的時鐘分配樹狀結構進行同步化。
使用指南: PDF | HTML
要求
支援軟體

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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模擬型號

LMX1906-SP IBIS Model

SNAM300.ZIP (61 KB) - IBIS Model
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設計工具

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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