產品詳細資料

Frequency (max) (MHz) 22600 Frequency (min) (MHz) 45 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -134 Features Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Ultra-fast VCO Calibration, Wideband Current consumption (mA) 500 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
Frequency (max) (MHz) 22600 Frequency (min) (MHz) 45 Normalized PLL phase noise (dBc/Hz) -236 1/f noise (10-kHz offset at 1-GHz carrier) (dBc/Hz) -134 Features Integer-boundary spurs (IBS) removal, Integrated VCO, JESD204B SYSREF, Multi-device sync, Phase adjustment, Ultra-fast VCO Calibration, Wideband Current consumption (mA) 500 Integrated VCO Yes Operating temperature range (°C) -40 to 85 Rating Catalog Lock time (µs) (typ) (s) Loop BW dependent
VQFNP (RTC) 48 49 mm² (7 mm × 7 mm)
  • Output frequency: 45 MHz to 22.6 GHz
  • 36-fs rms jitter (12 kHz – 95 MHz) at 6 GHz
  • High-performance PLL
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –134 dBc/Hz
    • -95 dBc Integer Mode Spurs (fPD=100 MHz)
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • Programmable input multiplier
    • Direct PFD input for offset mixing support allowing PLL N divider to be one for ultra-low jitter
  • 2.5-µs fast VCO calibration time
  • Mute pin with 200-ns mute/unmute time
  • –45-dBc VCO leakage with doubler enabled
  • Support for external VCO up to 22.6-GHz
  • Synchronization of output phase across multiple devices
  • Two differential RF outputs and one differential SYSREF output for JESD204B support
  • Output frequency: 45 MHz to 22.6 GHz
  • 36-fs rms jitter (12 kHz – 95 MHz) at 6 GHz
  • High-performance PLL
    • Figure of merit: –236 dBc/Hz
    • Normalized 1/f noise: –134 dBc/Hz
    • -95 dBc Integer Mode Spurs (fPD=100 MHz)
    • High phase detector frequency
      • 400-MHz integer mode
      • 300-MHz fractional mode
    • Programmable input multiplier
    • Direct PFD input for offset mixing support allowing PLL N divider to be one for ultra-low jitter
  • 2.5-µs fast VCO calibration time
  • Mute pin with 200-ns mute/unmute time
  • –45-dBc VCO leakage with doubler enabled
  • Support for external VCO up to 22.6-GHz
  • Synchronization of output phase across multiple devices
  • Two differential RF outputs and one differential SYSREF output for JESD204B support

The LMX2820 is a high-performance, wideband synthesizer that can generate any frequency in the range of 45 MHz to 22.6 GHz. The high performance PLL with figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2820 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The fast calibration algorithm greatly reduces the VCO calibration time, enabling systems requiring fast frequency hopping. The LMX2820 can generate or repeat SYSREF that is compliant to the JESD204B standard, allowing for its use as a low-noise clock source for high-speed data converters. This synthesizer can also be used with an external VCO. A direct PFD input pin is provided to support offset mixing for low spurious transmission.

The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for onboard low-noise LDOs.

The LMX2820 is a high-performance, wideband synthesizer that can generate any frequency in the range of 45 MHz to 22.6 GHz. The high performance PLL with figure of merit of –236 dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2820 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. The fast calibration algorithm greatly reduces the VCO calibration time, enabling systems requiring fast frequency hopping. The LMX2820 can generate or repeat SYSREF that is compliant to the JESD204B standard, allowing for its use as a low-noise clock source for high-speed data converters. This synthesizer can also be used with an external VCO. A direct PFD input pin is provided to support offset mixing for low spurious transmission.

The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for onboard low-noise LDOs.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 LMX2820 22.6-GHz Wideband PLLatinum RF Synthesizer With Phase Synchronization and JESD204B Support datasheet (Rev. C) PDF | HTML 2021/2/4
應用說明 Leveraging TI’s Clock Tools For Converter Designs PDF | HTML 2026/4/20
應用說明 Using Instant Calibration With the LMX2820 PDF | HTML 2025/6/14
應用說明 Practical Clocking Considerations That Give Your Next High-Speed Converter Design an Edge (Rev. A) PDF | HTML 2025/4/11
應用說明 Combining More than Two Signals for Better Noise PDF | HTML 2025/3/24
Application brief Compilation of RF Synthesizer Resources PDF | HTML 2024/10/22
應用說明 Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 2024/9/3
Circuit design MASH_SEED Optimization and Impact on Spurs (LMX2820) PDF | HTML 2024/8/8
Application brief Common Mistakes While Designing With Rf Clock Synthesizers and How To Mitigate the Same PDF | HTML 2024/8/8
Application brief High-Frequency Clock (> 20GHz) Skew Variation Between Two RF Synthesizers Across Temperature PDF | HTML 2024/4/26
Application brief High-Frequency Delay Adjustments Between Two RF Synthesizers PDF | HTML 2024/4/26
Application brief LMX2820 with Internal Doubler versus LMX2594 PDF | HTML 2024/1/16
應用說明 LMX2820 RF Synthesizer Phase Noise Improvement With Alternative Topologies (Rev. A) PDF | HTML 2023/5/22
應用說明 External Doubler Extends LMX2820 Operation to 44 GHz PDF | HTML 2023/3/31
使用指南 How to Phase Synchronize Multiple LMX2820 Devices PDF | HTML 2022/12/19
應用說明 High Isolation, Fast Frequency Switching With LMX2820 in Ping-Pong Architecture PDF | HTML 2022/9/20
應用說明 Combining Two LMX2820 Synthesizer Outputs for Improved Phase Noise (Rev. A) PDF | HTML 2022/3/3
使用指南 LMX2820 Register Map (Rev. A) 2020/12/9
應用說明 Impact of PLL Jitter to GSPS ADC's SNR and Performance Optimization 2020/11/11
應用說明 Dramatically Improve Your Lock Time with VCO Instant Calibration PDF | HTML 2020/9/17
證書 LMX2820EVM EU Declaration of Conformity (DoC) 2020/6/9

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使用指南: PDF | HTML
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SNAM245.ZIP (45 KB) - IBIS 模型
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