首頁 時鐘與計時 時鐘產生器
首頁
時鐘與計時
時鐘產生器

PLL1708

現行

4.096 至 36.864-MHz、序列控制的 3.3-V 雙 PLL 多時產生器

立即訂購
產品規格表

PLL1708

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 4 Output type LVCMOS Output frequency (max) (MHz) 0.096 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS Operating temperature range (°C) -25 to 85 Features 3.3-V VCC/VDD Rating Catalog
Number of outputs 4 Output type LVCMOS Output frequency (max) (MHz) 0.096 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS Operating temperature range (°C) -25 to 85 Features 3.3-V VCC/VDD Rating Catalog
SSOP (DBQ) 20 51.9 mm² (8.65 mm × 6 mm)
  • 27-MHz Master Clock Input
  • Generated Audio System Clock (PLL1707):
    • SCKO0: 768 fS (fS = 44.1 kHz)
    • SCKO1: 768 fS, 512 fS (fS = 48 kHz)
    • SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
    • SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
  • Generated Audio System Clock (PLL1708):
    • SCKO0: 768 fS (fS = 44.1 kHz)
    • SCKO1: 768 fS, 512 fS, 384 fS , 256 fS (fS = 48 kHz)
    • SCKO2: 256 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz)
    • SCKO3: 384 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz)
  • Zero PPM Error Output Clocks
  • Low Clock Jitter: 50 ps (Typical)
  • Multiple Sampling Frequencies (PLL1707):
    • fS = 32, 44.1, 48, 64, 88.2, 96 kHz
  • Multiple Sampling Frequencies (PLL1708):
    • fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz
  • 3.3-V Single Power Supply
  • PLL1707: Parallel Control
    PLL1708: Serial Control
  • Package: 20-Pin SSOP (150 mil), Lead-Free Product
  • APPLICATIONS
    • HDD + DVD Recorders
    • DVD Recorders
    • HDD Recorders
    • DVD Players
    • DVD Add-On Cards for Multimedia PCs
    • Digital HDTV Systems
    • Set-Top Boxes

The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.
  • 27-MHz Master Clock Input
  • Generated Audio System Clock (PLL1707):
    • SCKO0: 768 fS (fS = 44.1 kHz)
    • SCKO1: 768 fS, 512 fS (fS = 48 kHz)
    • SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
    • SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
  • Generated Audio System Clock (PLL1708):
    • SCKO0: 768 fS (fS = 44.1 kHz)
    • SCKO1: 768 fS, 512 fS, 384 fS , 256 fS (fS = 48 kHz)
    • SCKO2: 256 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz)
    • SCKO3: 384 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz)
  • Zero PPM Error Output Clocks
  • Low Clock Jitter: 50 ps (Typical)
  • Multiple Sampling Frequencies (PLL1707):
    • fS = 32, 44.1, 48, 64, 88.2, 96 kHz
  • Multiple Sampling Frequencies (PLL1708):
    • fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz
  • 3.3-V Single Power Supply
  • PLL1707: Parallel Control
    PLL1708: Serial Control
  • Package: 20-Pin SSOP (150 mil), Lead-Free Product
  • APPLICATIONS
    • HDD + DVD Recorders
    • DVD Recorders
    • HDD Recorders
    • DVD Players
    • DVD Add-On Cards for Multimedia PCs
    • Digital HDTV Systems
    • Set-Top Boxes

The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.

The PLL1707 are low cost, phase-locked loop (PLL) multiclock generators. The PLL1707 and PLL1708 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins and those of the PLL1708 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1707 and PLL1708 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD recorders, HDD recorders, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes.

The PLL1707 are low cost, phase-locked loop (PLL) multiclock generators. The PLL1707 and PLL1708 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins and those of the PLL1708 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1707 and PLL1708 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD recorders, HDD recorders, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes.
filter 尋找其它 時鐘產生器
下載 觀看有字幕稿的影片 影片

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 3.3 V Dual PLL Multi-Clock Generator datasheet 2002/12/2

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

封裝 針腳 CAD 符號、佔位空間與 3D 模型
SSOP (DBQ) 20 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片