開發模組 (EVM) 的 GUI
SN65LVCP1414
- Quad Channel, Uni-Directional, Multi-Rate,
Dual-Mode Linear Equalizer with Operation up
to 14.2Gbps Serial Data Rate for Backplane and
Cable Interconnects - Linear Equalization Increases Link Margin for
Systems Implementing Decision Feedback
Equalizers (DFE) - 17dB Analog Equalization at 7.1GHz with 1dB Step
Control for Backplane Mode or Cable Mode - Output Linear Dynamic Range: 1200mV
- Bandwidth: >20GHz – Typical
- Better than 15dB Return Loss at 7.1GHz
- Supports Out-of-Band (OOB) Signaling
- Low Power, Typically 80mW per Channel at 2.5V VCC
- 38-Terminal QFN (Quad Flatpack, No-Lead)
5 mm × 7 mm × 0.75 mm, 0.5 mm Terminal Pitch - Excellent Impedance Matching to 100Ω Differential PCB
Transmission Lines - GPIO or I2C Control
- 2.5V and 3.3V±5% Single Power Supply
- 2kV ESD (HBM)
- Flow-Through Pin-Out Provides Ease of Routing
- Small Package Size Saves Board Space
- Low Power
The SN65LVCP1414 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of the SN65LVCP1414 is designed to work with an ASIC or FPGA with digital equalization employing Decision Feedback Equalizers (DFE). The SN65LVCP1414 linear equalizer preserves the shape of the transmitted signal ensuring optimum DFE performance. The SN65LVCP1414 provides a low power solution while at the same time extending the effectiveness of DFE.
The SN65LVCP1414 is configurable via I2C or GPIO interface. Using the I2C interface of the SN65LVCP1414 enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all channels using the GPIO Input pins.
The SN65LVCP1414 outputs can be disabled independently via I2C.
The SN65LVCP1414 operates from a single 2.5V or 3.3V power supply.
The package for the SN65LVCP1414 is a 38 pin 5-mm × 7-mm × 0.75-mm QFN (Quad Flat-pack No-lead) lead-free package with 0.5mm pitch and is characterized for operation from –40°C to 85°C.
技術文件
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檢視所有 4 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 14.2-Gbps Quad Channel, Dual Mode Linear Equalizer datasheet (Rev. A) | 2014年 1月 17日 | |
| Application note | The Benefits of Using Linear Equalization in Backplane and Cable Applications | 2013年 1月 31日 | ||
| EVM User's guide | SN65LVCP1414 EVM User's Guide | 2012年 7月 2日 | ||
| User guide | SN65LVCP1414 Graphical User Interface Guide | 2012年 7月 2日 |
設計與開發
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使用指南: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (RLJ) | 38 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。