SN74ALS996
- 3-State I/O-Type Read-Back Inputs
- Bus-Structured Pinout
- T/C\ Determines True or Complementary Data at Q Outputs
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable () input is low. Data can be read back onto the data inputs by taking the read () input low, in addition to having low. When EN\ is high, both the read-back and write modes are disabled. Transitions on should only be made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by the polarity (T/C\) input. When T/C\ is high, Q is the same as is stored in the flip-flops. When T/C\ is low, the output data is inverted. The Q outputs can be placed in the high-impedance state by taking the output-enable () input high. does not affect the internal operation of the register. Old data can be retained or new data can be entered while the outputs are off.
A low level at the clear () input resets the internal registers low. The clear function is asynchronous and overrides all other register functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOL for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS996 is characterized for operation from 0°C to 70°C.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 8-Bit D-Type Edge-Triggered Read-Back Latches datasheet (Rev. B) | 1995年 1月 1日 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 | |
Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||
Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
Application note | Live Insertion | 1996年 10月 1日 | ||
Application note | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
設計與開發
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14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (DW) | 24 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點