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SN74SSTVF16857

現行

具 SSTL_2 輸入和輸出的 14 位元暫存緩衝器

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產品規格表

SN74SSTVF16857

現行
產品規格表 立即訂購

產品詳細資料

Number of outputs 14 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Operating temperature range (°C) 0 to 70 Rating Catalog Output type SSTL-18 Input type SSTL-18
Number of outputs 14 Core supply voltage (V) 2.5 Output supply voltage (V) 2.5 Operating temperature range (°C) 0 to 70 Rating Catalog Output type SSTL-18 Input type SSTL-18
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16857
  • 600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM Applications
  • Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
  • Pinout and Functionality Compatible With JEDEC Standard SSTV16857
  • 600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM Applications
  • Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load
  • Outputs Meet SSTL_2 Class I Specifications
  • Supports SSTL_2 Data Inputs
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.

This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.

The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.

The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet SN74SSTVF16857 datasheet (Rev. B) 2003年 4月 3日
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note 56-Pin Quad Flatpack No-Lead Logic Package 2003年 2月 7日
Application note Application of the SN74SSTVF16857 in Planar PC2700 (DDR-333) RDIMMs 2003年 1月 10日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature DIMM Module Solution 2002年 6月 13日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note Application of the SN74SSTV32852 in Stacked, Low-Profile (1U) PC-1600/2100 DIMMs 2001年 11月 7日
Application note Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859 2001年 2月 9日

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模擬型號

HSPICE Model of SN74SSTVF16857

SCEJ141.ZIP (45 KB) - HSpice Model
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模擬型號

SN74SSTVF16857 IBIS Model

SCEM271.ZIP (17 KB) - IBIS Model
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