TMS320C6474

現行

多核數位訊號處理器

立即訂購

產品規格表

document-pdfAcrobat TMS320C6474 Multicore Digital Signal Processor Data Manual datasheet (Rev. H) (英文)

TMS320C6474

現行

產品規格表

立即訂購

產品詳細資料

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 95

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 95

FCBGA (CUN)

561

529 mm² (23 mm × 23 mm)

Key Features
- High-Performance Multicore DSP (C6474)
- Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
- Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
- Commercial Temperature and Extended Tmperature
- 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
- Enhanced VCP2/TCP2
- Frame Synchronization Interface
- 16-/32-Bit DDR2-667 Memory Controller
- EDMA3 Controller
- Antenna Interface
- Two 1x Serial RapidIO® Links, v1.2 Compliant
- One 1.8-V Inter-Integrated Circuit (I2C) Bus
- Two 1.8-V McBSPs
- 1000 Mbps Ethernet MAC (EMAC)
- Six 64-Bit General-Purpose Timers
- 16 General-Purpose I/O (GPIO) Pins
- Internal Semaphore Module non-UMTS Systems
- System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
High-Performance Multicore DSP (C6474)
- Instruction Cycle Time:
  - 1.2-GHz Device: 1.0-ns to 0.83-ns
  - 1-GHz Device: 1-ns
  - 850-MHz Device: 1.18 ns
- Clock Rate:
  - 1.2-GHz Device: 1-GHz to 1.2-GHz
  - 1-GHz Device: 1-GHz
  - 850-MHz Device: 850 MHz
- Eight 32-Bit Instructions/Cycle
- Commercial Temperature:
  - 1.2-GHz Device: 0°C to 95°C
  - 1-GHz Device: 0°C to 100°C
  - 850-MHZ and 1-GHz Device: 0°C to 100°C
- Extended Temperature:
  - 1.2-GHz Device: -40°C to 95°C⁽¹⁾
  - 1-GHz Device: -40°C to 100°C
3 TMS320C64x+™ DSP Cores
- Dedicated SPLOOP Instructions
- Compact Instructions (16-Bit)
- Exception Handling
TMS320C64x+ Megamodule L1/L2 Memory Architecture
- 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
- 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
- 512 K-Bit (64 K-Byte) L3 ROM
Enhanced VCP2
- Supports Over 694 7.95-Kbps AMR
Enhanced Turbo Decoder Coprocessor (TCP2)
- Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
Endianness: Little Endian, Big Endian
Frame Synchronization Interface
- Time Alignment Between Internal Subsystems, External Devices/System
- OBSAI RP1 Compliant for Frame Burst Data
- Alternate Interfaces for non-RP1 and non-UMTS Systems
16-/32-Bit DDR2-667 Memory Controller
EDMA3 Controller (64 Independent Channels)
Antenna Interface
- 6 Configurable Links (Full Duplex)
- Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
- Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
- Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
Two 1x Serial RapidIO® Links, v1.2 Compliant
- 1.25-, 2.5-, 3.125-Gbps Link Rates
- Message Passing and DirectIO Support
- Error Management Extensions and Congestion Control
One 1.8-V Inter-Integrated Circuit (I2C) Bus
Two 1.8-V McBSPs
1000 Mbps Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Supports SGMII, v1.8 Compliant
- 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
Six 64-Bit General-Purpose Timers
- Configurable up to Twelve 32-Bit Timers
- Configurable in a Watchdog Timer mode
16 General-Purpose I/O (GPIO) Pins
Internal Semaphore Module
- Software Method to Control Access to Shared Resources
- 32 General Purpose Semaphore Resources
System PLL and PLL Controller
DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
0.065-µm/7-Level Cu Metal Process (CMOS)
SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
1.8-V, 1.1-V I/Os

⁽¹⁾Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.

Key Features
- High-Performance Multicore DSP (C6474)
- Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
- Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
- Commercial Temperature and Extended Tmperature
- 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
- Enhanced VCP2/TCP2
- Frame Synchronization Interface
- 16-/32-Bit DDR2-667 Memory Controller
- EDMA3 Controller
- Antenna Interface
- Two 1x Serial RapidIO® Links, v1.2 Compliant
- One 1.8-V Inter-Integrated Circuit (I2C) Bus
- Two 1.8-V McBSPs
- 1000 Mbps Ethernet MAC (EMAC)
- Six 64-Bit General-Purpose Timers
- 16 General-Purpose I/O (GPIO) Pins
- Internal Semaphore Module non-UMTS Systems
- System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
High-Performance Multicore DSP (C6474)
- Instruction Cycle Time:
  - 1.2-GHz Device: 1.0-ns to 0.83-ns
  - 1-GHz Device: 1-ns
  - 850-MHz Device: 1.18 ns
- Clock Rate:
  - 1.2-GHz Device: 1-GHz to 1.2-GHz
  - 1-GHz Device: 1-GHz
  - 850-MHz Device: 850 MHz
- Eight 32-Bit Instructions/Cycle
- Commercial Temperature:
  - 1.2-GHz Device: 0°C to 95°C
  - 1-GHz Device: 0°C to 100°C
  - 850-MHZ and 1-GHz Device: 0°C to 100°C
- Extended Temperature:
  - 1.2-GHz Device: -40°C to 95°C⁽¹⁾
  - 1-GHz Device: -40°C to 100°C
3 TMS320C64x+™ DSP Cores
- Dedicated SPLOOP Instructions
- Compact Instructions (16-Bit)
- Exception Handling
TMS320C64x+ Megamodule L1/L2 Memory Architecture
- 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
- 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
- 512 K-Bit (64 K-Byte) L3 ROM
Enhanced VCP2
- Supports Over 694 7.95-Kbps AMR
Enhanced Turbo Decoder Coprocessor (TCP2)
- Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
Endianness: Little Endian, Big Endian
Frame Synchronization Interface
- Time Alignment Between Internal Subsystems, External Devices/System
- OBSAI RP1 Compliant for Frame Burst Data
- Alternate Interfaces for non-RP1 and non-UMTS Systems
16-/32-Bit DDR2-667 Memory Controller
EDMA3 Controller (64 Independent Channels)
Antenna Interface
- 6 Configurable Links (Full Duplex)
- Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
- Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
- Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
Two 1x Serial RapidIO® Links, v1.2 Compliant
- 1.25-, 2.5-, 3.125-Gbps Link Rates
- Message Passing and DirectIO Support
- Error Management Extensions and Congestion Control
One 1.8-V Inter-Integrated Circuit (I2C) Bus
Two 1.8-V McBSPs
1000 Mbps Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Supports SGMII, v1.8 Compliant
- 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
Six 64-Bit General-Purpose Timers
- Configurable up to Twelve 32-Bit Timers
- Configurable in a Watchdog Timer mode
16 General-Purpose I/O (GPIO) Pins
Internal Semaphore Module
- Software Method to Control Access to Shared Resources
- 32 General Purpose Semaphore Resources
System PLL and PLL Controller
DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
0.065-µm/7-Level Cu Metal Process (CMOS)
SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
1.8-V, 1.1-V I/Os

⁽¹⁾Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

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重要文件	類型	標題	格式選項	日期
*	資料表	TMS320C6474 Multicore Digital Signal Processor Data Manual datasheet (Rev. H)		2011/4/11
*	勘誤表	TMS320C6474 DSP Silicon Errata (Silicon Revisions 2.1, 1.3, 1.2) (Rev. C)		2011/3/11
	應用說明	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	2021/5/19
	使用指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020/6/1
	應用說明	Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)		2013/7/19
	更多文件說明	Picture it: DSPs in medical imaging (Rev. C)		2013/7/12
	應用說明	Multicore Programming Guide (Rev. B)		2012/8/29
	使用指南	TMS320C6474 DSP EMAC/MDIO Module Reference Guide (Rev. B)		2012/3/2
	應用說明	Introduction to TMS320C6000 DSP Optimization		2011/10/6
	使用指南	TMS320C6474 DSP Enhanced DMA (EDMA3) Controller User's Guide (Rev. B)		2011/7/1
	使用指南	Bootloader User's Guide for the TMS320C645x/C647x DSP (Rev. G)		2011/6/3
	使用指南	TMS320C6474 DSP DDR2 Memory Controller User's Guide (Rev. D)		2011/6/2
	應用說明	Tuning VCP2 and TCP2 Bit Error Rate Performance		2011/2/11
	使用指南	TMS320C6474 Serial RapidIO (SRIO) User's Guide (Rev. D)		2011/2/3
	使用指南	TMS320C64x+ DSP Megamodule Reference Guide (Rev. K)		2010/8/3
	應用說明	TMS320C6474 Hardware Design Guide (Rev. B)		2010/8/3
	使用指南	TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J)		2010/7/30
	使用指南	TMS320C6474 DSP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. A)		2010/5/18
	使用指南	TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 Reference Guide (Rev. B)		2009/12/8
	使用指南	TMS320C6474 DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. A)		2009/10/28
	應用說明	Connecting Antenna Interface (AIF) With TDM Bridge Chip (IDT 80HFC001)		2009/8/28
	應用說明	Using the TMS320C6474 Antenna Interface (AIF) for Inter-DSP Communication		2009/8/28
	應用說明	Direct I/O Library		2009/8/28
	應用說明	TMS320C6474 DDR2 Implementation Guidelines (Rev. A)		2009/8/4
	應用說明	How to Approach Inter-Core Communication on TMS320C6474		2009/1/27
	應用說明	Inter-Core Communication on TMS320C6474		2009/1/12
	應用說明	TPS40197 Reference Design		2008/12/17
	白皮書	See the difference:DSPs in medical imaging		2008/10/31
	使用指南	TMS320C6474 DSP Power/Sleep Controller (PSC) User’s Guide		2008/10/14
	使用指南	TMS320C6474 DSP General-Purpose Input/Output (GPIO) User's Guide		2008/10/14
	應用說明	TMS320C6474 Common Bus Architecture (CBA) Throughput		2008/10/14
	使用指南	TMS320C6474 DSP 64-Bit Timer User's Guide		2008/10/14
	應用說明	TMS320C6474 Power Consumption Summary		2008/10/14
	使用指南	TMS320C6474 Antenna Interface User's Guide		2008/10/14
	應用說明	Migrating from TMS320C6455 to TMS320C6474		2008/10/14
	使用指南	TMS320C6474 Frame Synchronization User's Guide		2008/10/14
	使用指南	TMS320C6474 Semaphore User's Guide		2008/10/14
	使用指南	TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL) Controller UG		2008/10/14
	使用指南	TMS320C6474 DSP Chip Interrupt Controller (CIC) User's Guide		2008/10/14
	應用說明	TMS320C6474 Multicore Digital Signal Processor Technical Brief		2008/10/14
	使用指南	TMS320C6474 DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide		2008/10/14
	應用說明	TMS320C6474 Module Throughput Application Report		2008/10/14
	應用說明	TMS320C6474 SERDES Implementation Guidelines		2008/10/14
	應用說明	C6474 (x4) Power Using Modules		2008/10/1
	應用說明	C6474 (x2) Power Using Modules		2008/9/30
	應用說明	Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A)		2008/8/21
	應用說明	Migrating from TMS320C64x to TMS320C64x+ (Rev. A)		2005/10/20
	使用指南	High-Speed DSP Systems Design Reference Guide		2005/5/20

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XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

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TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

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TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH

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軟體開發套件 (SDK)

LINUXMCSDK — Linux MCSDK for C66x, C647x and C645x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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軟體開發套件 (SDK)

MEDIMGSTK-C66X — TI Embedded Processor Software Tool Kit for Medical Imaging (STK-MED) - for C66x and C64x+ based processors

The TI Embedded Processor Software Toolkit for Medical Imaging (STK-MED) is a collection of several standard ultrasound and optical coherence tomography (OCT) algorithms for TI’s C66x™ and C64x+™ architecture. The algorithms showcase how medical imaging functions can leverage the C66x and (...)

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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NDKTCPIP — TI-RTOS 網路

TI-RTOS Networking (formerly known as the NDK or Network Developers Kit) combines dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCUs as a part of TI-RTOS and also for high-performance TMS320C6000™ DSP-based devices.

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SPRC122 — C62x/C64x Fast Run-Time Support Library

C62x/64x FastRTS 庫是一款經過最佳化的浮點函式庫，適用於使用 TMS320C62x 或 TMS320C64x 裝置的 C 編程人員。這些常式通常用於計算密集型即時應用，在這些應用中，最佳執行速度至關重要。透過將當前的浮點庫 (RTS) 函式替換為 FastRTS 函式庫，您無需重寫現有的程式碼，即可顯著提高執行速度。

該版本還包括用於 FastRTS 庫提供的函式子集的 C 語言實作。C 程式碼允許使用者內嵌這些函式並獲得顯著改進的性能。

特色

單精度和雙精度數學函式	單精度和雙精度轉換函式
浮點加法	浮點數轉換為 32 位元有號整數
32 位元有號整數轉換為浮點數
浮點除法	浮點數轉換為 (...)

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SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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SPRC265 — TMS320C6000 DSP 函式庫 (DSPLIB)

TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

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SPRC542 — C64x+ IQMath 庫 - 虛擬浮點引擎

德州儀器 TMS320C64x+ IQmath 函式庫是高度最佳化的高精度數學函式庫集合，使 C/C++ 編程人員可以在 TMS320C64x+ 裝置上將浮點算法無縫植入定點程式碼中。這些常式通常用於計算密集型即時應用，在這些應用中，最佳執行速度與高精度至關重要。使用這些常式，您可以達到比標準 ANSI C 語言編寫的同等程式碼更快的執行速度。另外，透過提供即用型高精度函式，TI IQmath 函式庫可以大幅縮短 DSP 應用程式的開發時間。IQmath 函式庫版本也包括使用 IQmath 核心實作複數 FFT 和 FIR 核心的範例。

原始程式碼 - 透過內嵌 IQMath (...)

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SPRC975 — TMS320C6474 Chip Support Library

此適用於 TMS320C6474 的 CSL v3 版本包含 C6474 模組的週邊設備編程（功能與暫存器層級）API。此版本中支援的模組清單列於下載安裝程式所包含的發行說明中。這組 API 提供可由更高層級軟體使用的週邊設備抽象。

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驅動程式或資料庫

TELECOMLIB — 電信和媒體庫 - 用於 TMS320C64x+ 和 TMS320C55x 處理器的 FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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軟體轉碼器

C64XPLUSCODECS — 轉碼器 - 音訊、視訊、語音 - 基於 C64x+ 的裝置 (OMAP35x、C645x、C647x、DM646、DM644x、DM643x)

TI 轉碼器免費提供，附帶生產授權，且可供立即下載。全部經過生產測試，可輕鬆整合到視訊和語音應用之中。按一下 GET SOFTWARE (取得軟體) 按鈕 (上方) 以存取經過測試的最新轉碼器版本。該頁面及每個安裝程式中都包含產品規格表和版本說明。

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軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

從：Adaptive Digital Technologies, Inc.

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