TPS65916
- System Voltage Range from 3.135 V to 5.25 V
- Low-Power Consumption
- 20 µA in Off Mode
- 90 µA in Sleep Mode With Two SMPSs Active
-
Five Step-Down Switched-Mode Power Supply (SMPS) Regulators:
- 0.7- to 3.3-V Output Range in 10- or 20-mV Steps
- Two SMPS Regulators With 3.5-A Capability, With the Ability to Combine into 7-A Output in Dual-Phase Configuration, With Differential Remote Sensing (Output and Ground)
- Three Other SMPS Regulators with 3-A, 2-A, and 1.5-A Capabilities
- Dynamic Voltage Scaling (DVS) Control and Output Current Measurement in 3.5-A and 3-A SMPS Regulators
- Hardware and Software Controlled Eco-mode™ Supplying up to 5 mA
- Short-Circuit Protection
- Power-Good Indication (Voltage and Overcurrent Indication)
- Internal Soft-Start for In-Rush Current Limitation
- Ability to Synchronize to External Clock between 1.7 MHz and 2.7 MHz
- Five Low-Dropout (LDO) Linear Regulators:
- 0 .9- to 3.3-V Output Range in 50-mV steps
- Two With 300-mA Capability and Bypass Mode
- One With 100-mA Capability and Capable of Low-Noise Performance up to 50 mA
- Two Other LDOs With 200-mA Current Capability
- Short-Circuit Protection
- 12-Bit Sigma-Delta General-Purpose ADC (GPADC) With 8 Input Channels (2 external)
- Thermal Monitoring With High Temperature Warning and Thermal Shutdown
- Power Sequence Control:
- Configurable Power-Up and Power-Down Sequences (OTP)
- Configurable Sequences Between the SLEEP and ACTIVE State Transition (OTP)
- Three Digital Output Signals that can be Included in the Startup Sequence
- Selectable Control Interface:
- One SPI for Resource Configurations and DVS Control
- Two
I2C Interfaces.
- One Dedicated for DVS Control
- One General Purpose I2C Interface for Resource Configuration and DVS Control
- OTP Bit-Integrity Error Detection With Options to Proceed or Hold Power-Up Sequence and RESET_OUT Release
- Package Option:
- 7-mm × 7-mm 48-pin VQFN With 0.5-mm Pitch
The TPS65916 PMIC integrates five configurable step-down converters with up to 3.5 A of output current to power the processor core, memory, I/O, and preregulation of LDOs The step-down converters are synchronized to an internal 2.2-MHz clock to improve EMC performance of the device. The GPIO_3 pin allows the step-down converters to synchronize to an external clock, allowing multiple devices to synchronize to the same clock which improves system-level EMC performance. The device also contains five LDOs to power low-current or low-noise domains.
The power-sequence controller uses one-time programmable (OTP) memory to control the power sequences, as well as default configurations such as output voltage and GPIO configurations. The OTP is factory-programmed to allow start-up without any software required. Most static settings can be changed from the default through SPI or I2C to configure the device to meet many different system needs. For example, voltage-scaling registers are used to support dynamic voltage-scaling requirements of processors. The OTP also contains a bit-integrity-error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting in an unknown state.
The TPS65916 device also includes an analog-to-digital converter (ADC) to monitor the system state. The GPADC includes two external channels to monitor any external voltage, as well as internal channels to measure supply voltage, output current, and die temperature, allowing the processor to monitor the health of the system. The device offers a watchdog to monitor for software lockup, and includes protection and diagnostic mechanisms such as short-circuit protection, thermal monitoring, shutdown, and automatic ADC conversions to detect if a voltage is below a predefined threshold. The PMIC can notify the processor of these events through the interrupt handler, allowing the processor to take action in response.
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技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS65916 3.1-V to 5.2-V, 5 Buck Converter and 5 LDO Power Management IC (PMIC) datasheet (Rev. C) | PDF | HTML | 2018/8/20 | ||
| * | 使用指南 | TPS65916 Register Map (Rev. A) | 2017/4/11 | |||
| 應用說明 | POR Generation in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 Devices (Rev. A) | 2018/9/21 | ||||
| 應用說明 | TPS65917 Power Estimation Tool (Rev. B) | 2018/6/14 | ||||
| 使用指南 | TPS65916 User's Guide to Power AM570x (Rev. A) | 2018/5/7 | ||||
| 使用指南 | TPS65916 User’s Guide to Power AM571x (Rev. D) | 2018/5/7 | ||||
| 應用說明 | Guide to Using the GPADC in TPS65903x, TPS65917-Q1, TPS65919-Q1, and TPS65916 de (Rev. A) | 2017/12/13 | ||||
| 技術文章 | How to implement remote sense in your PMIC | PDF | HTML | 2016/11/17 | |||
| 技術文章 | Using PMICs to support a wide range of power sequencing requirements | PDF | HTML | 2016/11/1 | |||
| 應用說明 | TPS65916 Design Checklist | 2016/8/22 | ||||
| 應用說明 | Adaptive (Dynamic) Voltage (Frequency) Scaling – Motivation and Implementations | 2014/3/28 |
設計與開發
電源供應解決方案
探索包括 TPS65916 的解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。
TPS65916EVM — TPS65916 電源管理 IC 評估模組
TPS65916 是一款針對汽車應用設計的整合式電源管理積體電路 (PMIC)。 該裝置提供五個可配置的降壓轉換器，每個輸出電流最高可達 3.5A，適用於記憶體供電、處理器核心電源、輸入/輸出 (I/O) 電源，或作為 LDO 的前級調整。 TPS65916 也包含 5 個供外部使用的 LDO。
TIDEP-0100 — AM570x 6 層 PCB 參考設計
TIPA-050027 — 適用於工業應用，採用 TPS65916 PMIC 的 AM571 電源供應設計
此電源供應設計說明可為 AM57x 處理器供電的最佳化電源管理 IC (PMIC)。使用指南可作為 TPS65916 PMIC 與 AM571x 處理器間連線的指引。本指南說明平台連線、開/關機和熱重設順序，以及 OTP 配置。
TIPA-050030 — 適用於工業應用，採用 TPS65916 PMIC 的 AM570 電源供應設計
此電源供應器設計說明可為 AM57x 處理器供電的最佳化電源管理 IC (PMIC)。使用指南可作為 TPS65916 PMIC 與 AM570x 處理器間連線的指引。本指南說明平台連線、開/關機和熱重設順序，以及 OTP 配置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。