UCC21550-Q1
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Universal: dual low-side, dual high-side or halfbridge driver
- AEC-Q100 qualified with the following results
- Device temperature grade 1
- Junction temperature range –40 to +150°C
- Up to 4A peak source and 6A peak sink output
- Common-mode transient immunity (CMTI) greater than 125V/ns
- Up to 25V VDD output drive supply
- 5V,8V,12V VDD UVLO options
- Switching parameters:
- 33ns typical propagation delay
- 5ns maximum pulse-width distortion
- 10µs maximum VDD power-up delay
- UVLO protection for all power supplies
- Fast disable for power sequencing
The UCC21550-Q1 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors.
The UCC21550-Q1 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).
Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.
With all these advanced features, the UCC21550-Q1 device enables high efficiency, high power density, and robustness in a wide variety of power applications.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | UCC21550x-Q1 Automotive 4A, 6A, Reinforced Isolation Dual-Channel Gate Driver datasheet (Rev. D) | PDF | HTML | 2024年 8月 9日 |
| Certificate | VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. Z) | 2026年 1月 8日 | ||
| Certificate | CQC Certificate for UCC21551xx | 2024年 8月 27日 |
設計與開發
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UCC21520EVM-286 — UCC21520 4A/6A 隔離式雙通道閘極驅動器評估模組
UCC21520EVM-286 專為評估 UCC21520DW 而設計,這是一款具備 4 A 源極和 6-A 汲極峰值電流能力的隔離式雙通道閘極驅動器。此 EVM 可做為驅動功率 MOSFETS、IGBTS 和 SiC MOSFETS 的參考設計,並提供 UCC21520 針腳功能識別、元件選擇指南與 PCB 配置範例。
Application Guide: Dual-Channel Schematic and Layout Design Guidelines (Rev. A)
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (DW) | 16 | Ultra Librarian |
| SOIC (DWK) | 14 | Ultra Librarian |
訂購與品質
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