The ADC08DJ3200 evaluation module (EVM) allows for the evaluation of the ADC08DJ3200 device. ADC08DJ3200 is a low-power, 8-bit, dual-channel 3.2-GSPS or single-channel 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable numerically-controlled oscillator (NCO) and decimation settings, which features a JESD204B interface.
The ADC08JD3200EVM has transformer-coupled analog inputs to accommodate a wide range of signal sources and frequencies. An LMX2582 clock synthesizer and LMK04828 JESD204B clock generator are included on the EVM and can be configured to provide an ultra-low-jitter ADC device clock and SYSREF for a complete JESD204B subclass 1 clocking solution.
The ADC08DJ3200EVM connects directly to TSW14J57EVM data capture hardware via the high-speed FMC+ connector. High-Speed Data Converter Pro Software (DATACONVERTERPRO-SW) is also available for data capture and analysis support when using the TSW14J57EVM.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | EVM User's guide | ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) | 09 Jan 2018 | |
| Data sheet | ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) | PDF | HTML | 21 Feb 2019 | |
| Certificate | ADC08DJ3200EVM EU Declaration of Conformity (DoC) | 02 Jan 2019 | ||
| More literature | Xilinx KCU105 + ADC12DJ3200 JMODE0/JMODE2 Design Firmware | 30 Aug 2017 | ||
| More literature | Arria10 + ADC12DJ3200 JMODE0 Design Firmware | 25 May 2017 |
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