Firmware
ADC12DJ3200
12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)
Data sheet
ADC12DJ3200
- ADC core:
- 12-bit resolution
- Up to 6.4 GSPS in single-channel mode
- Up to 3.2 GSPS in dual-channel mode
- Performance specifications:
- Noise floor (no signal, VFS = 1.0 VPP-DIFF):
- Dual-channel mode: –151.8 dBFS/Hz
- Single-channel mode: –154.6 dBFS/Hz
- HD2, HD3: –65 dBc up to 3 GHz
- Noise floor (no signal, VFS = 1.0 VPP-DIFF):
- Buffered analog inputs with VCMI of 0 V:
- Analog input bandwidth (–3 dB): 8.0 GHz
- Usable input frequency range: >10 GHz
- Full-scale input voltage (VFS, default): 0.8 VPP
- Analog input common-mode (VICM): 0 V
- Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19-fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204B serial data interface:
- Supports subclass 0 and 1
- Maximum lane rate: 12.8 Gbps
- Up to 16 lanes allows reduced lane rate
- Digital down-converters in dual-channel mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
- Four independent 32-Bit NCOs per DDC
- Power consumption: 3 W
- Power supplies: 1.1 V, 1.9 V
The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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Technical documentation
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View all 9 | Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | ADC12DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) | PDF | HTML | 21 Feb 2019 |
| Technical article | Keys to quick success using high-speed data converters | 13 Oct 2020 | ||
| User guide | ADC12DJ3200EVMCVAL with Alpha Data Xilinx® Kintex Ultrascale Space Dev. Kit (Rev. A) | PDF | HTML | 27 Aug 2020 | |
| Technical article | So, what's a VNA anyway? | 23 Aug 2019 | ||
| Technical article | So, what's the deal with frequency response? | 23 Aug 2019 | ||
| Technical article | Step-by-step considerations for designing wide-bandwidth multichannel systems | 04 Jun 2019 | ||
| Application notes | Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design | 30 May 2018 | ||
| EVM User's guide | ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) | 09 Jan 2018 | ||
| Analog Design Journal | Designing a modern power supply for RF sampling converters | 26 Apr 2017 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
Evaluation board
ADC12DJ3200EVM — ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module
The ADC12DJ3200 evaluation module (EVM) allows for the evaluation of device ADC12DJ3200. The ADC12DJ3200 is a low-power, 12-bit, dual 3.2-GSPS/single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with programmable NCO and (...)
User guide: PDF
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