Firmware
ADC12DJ3200
12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)
Data sheet
ADC12DJ3200
- ADC core:
- 12-bit resolution
- Up to 6.4 GSPS in single-channel mode
- Up to 3.2 GSPS in dual-channel mode
- Performance specifications:
- Noise floor (no signal, VFS = 1.0 VPP-DIFF):
- Dual-channel mode: –151.8 dBFS/Hz
- Single-channel mode: –154.6 dBFS/Hz
- HD2, HD3: –65 dBc up to 3 GHz
- Noise floor (no signal, VFS = 1.0 VPP-DIFF):
- Buffered analog inputs with VCMI of 0 V:
- Analog input bandwidth (–3 dB): 8.0 GHz
- Usable input frequency range: >10 GHz
- Full-scale input voltage (VFS, default): 0.8 VPP
- Analog input common-mode (VICM): 0 V
- Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19-fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204B serial data interface:
- Supports subclass 0 and 1
- Maximum lane rate: 12.8 Gbps
- Up to 16 lanes allows reduced lane rate
- Digital down-converters in dual-channel mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
- Four independent 32-Bit NCOs per DDC
- Power consumption: 3 W
- Power supplies: 1.1 V, 1.9 V
The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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Technical documentation
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Evaluation board
ADC12DJ3200EVM — ADC12DJ3200 12-bit, dual 3.2GSPS or single 6.4GSPS, RF-sampling ADC evaluation module
The ADC12DJ3200 evaluation module (EVM) is designed to evaluate the ADC12DJ3200 family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12DJ3200, a 12-bit, dual-channel 3.2GSPS or single-channel 6.4GSPS ADC with JESD204B interface and allows for evaluation of all (...)
User guide: PDF
Evaluation board
ABACO-3P-FMC134 — Abaco Systems® direct RF-conversion 4-channel 3.2-GSPS or 2-channel 6.4-GSPS ADC FPGA mezzanine card
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ANNAP-3P-WWDM60 — Annapolis Microsystems 4-channel ADC, 2-channel DAC FPGA mezzanine card up to 10GSPS
This high performance WILD FMC+ DM60 ADC & DAC has two input bandwidth options, internal sample clock options and internal 10MHz reference clock options. The WWDM60 has a choice of speed grades that utilize the ADC12DJ2700, ADC12DJ3200 and ADC12DJ5200RF up to 10GSPS. It allows for ADC and DAC (...)
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Accelerate your project by considering a complete off-the-shelf board that utilizes the ADC12DJ3200. The Pentek Jade® Model 71141 is an ideal radar and software radio interface solution that includes the Texas Instrument's ADC12DJ3200 ADC. The solution from Pentek provides a one-channel 6.4GSPS (...)
From: Pentek Inc.
Firmware
SLVC698 — Xilinx KCU105 + ADC12DJ3200 JMODE0/JMODE2 Design Firmware
Supported products & hardware
Firmware
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Supported products & hardware
GUI for evaluation module (EVM)
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
Supported products & hardware
GUI for evaluation module (EVM)
SLAC745 — ADC12DJxx00 GUI
Supported products & hardware
Simulation model
ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model
SLVMDV3.ZIP (47828 KB) - IBIS-AMI Model
Calculation tool
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Calculation tool
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PSPICE-FOR-TI — PSpice® for TI design and simulation tool
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TIDA-01023 — High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
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Reference designs
TIDA-01442 — Direct RF-Sampling Radar Receiver for L-, S-, C-, and X-Band Using ADC12DJ3200 Reference Design
This reference design uses the ADC12DJ3200 evaluation module (EVM) to demonstrate a direct RF-sampling receiver for a radar operating in HF, VHF, UHF, L-, S-, C- and part of X-band. The wide analog-input bandwidth and high-sampling rate (6.4 GSPS) of the analog-to-digital converter (ADC) provides (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
| FCCSP (ZEG) | 144 | Ultra Librarian |
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