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High-speed ADCs (≥10 MSPS)

ADC08DJ3200

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8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)

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Data sheet

ADC08DJ3200

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2800 Architecture Folding Interpolating SNR (dB) 49.4 ENOB (Bps) 7.8 SFDR (dB) 69 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2800 Architecture Folding Interpolating SNR (dB) 49.4 ENOB (Bps) 7.8 SFDR (dB) 69 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 1E+2 mm² 1E+1 x 1E+1
  • ADC core:
    • 8-bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Performance specifications (fIN = 997 MHz):
    • ENOB: 7.8 bits
    • SFDR:
      • Dual-channel mode: 67 dBFS
      • Single-channel mode: 62 dBFS
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Power consumption: 2.8 W
  • Power supplies: 1.1 V, 1.9 V
  • ADC core:
    • 8-bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Performance specifications (fIN = 997 MHz):
    • ENOB: 7.8 bits
    • SFDR:
      • Dual-channel mode: 67 dBFS
      • Single-channel mode: 62 dBFS
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Power consumption: 2.8 W
  • Power supplies: 1.1 V, 1.9 V

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.
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Technical documentation

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Type Title Date
* Data sheet ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 21 Feb 2019
Application notes Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design 30 May 2018
EVM User's guide ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) 09 Jan 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC08DJ3200EVM — ADC08DJ3200 8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling ADC Evaluation Module

The ADC08DJ3200 evaluation module (EVM) allows for the evaluation of the ADC08DJ3200 device. ADC08DJ3200 is a low-power, 8-bit, dual-channel 3.2-GSPS or single-channel 6.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with (...)

User guide: PDF
Not available on TI.com
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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GUI for evaluation module (EVM)

ADC12DJxx00 GUI (Rev. A)

SLAC745A.ZIP (177821 KB)
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Simulation model

ADC12DJ3200 IBIS Model

SLVMC42.ZIP (36 KB) - IBIS Model
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Simulation model

ADC12DJ3200 IBIS-AMI Model

SLVMC55.ZIP (5569 KB) - IBIS-AMI Model
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Calculation tool

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-01022 — Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-01021 — Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers

High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
Design guide: PDF
Schematic: PDF
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FCCSP (AAV) 144 View options
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