ADC08DJ3200 8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC) | TI.com

ADC08DJ3200
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8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)

8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC) - ADC08DJ3200
Datasheet
ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet
 

Description

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.

Features

  • ADC Core:
    • 8-Bit Resolution
    • Up to 6.4 GSPS in Single-Channel Mode
    • Up to 3.2 GSPS in Dual-Channel Mode
  • Performance Specifications (fIN = 997 MHz):
    • ENOB: 7.8 Bits
    • SFDR:
      • Dual-Channel Mode: 67 dBFS
      • Single-Channel Mode: 62 dBFS
  • Buffered Analog Inputs With VCMI of 0 V:
    • Analog Input Bandwidth (–3 dB): 8.0 GHz
    • Usable Input Frequency Range: >10 GHz
    • Full-Scale Input Voltage (VFS, Default): 0.8 VPP
    • Analog Input Common-Mode (VICM): 0 V
  • Noiseless Aperture Delay (TAD) Adjustment:
    • Precise Sampling Control: 19-fs Step
    • Simplifies Synchronization and Interleaving
    • Temperature and Voltage Invariant Delays
  • Easy-to-Use Synchronization Features:
    • Automatic SYSREF Timing Calibration
    • Timestamp for Sample Marking
  • JESD204B Serial Data Interface:
    • Supports Subclass 0 and 1
    • Maximum Lane Rate: 12.8 Gbps
    • Up to 16 Lanes Allows Reduced Lane Rate
  • Power Consumption: 2.8 W
  • Power Supplies: 1.1 V, 1.9 V

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Parametrics

Compare all products in High-speed ADCs (>10MSPS) Email Download to Excel
Part number Order Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADC08DJ3200 Order now 3200
6400    		 Ultra High Speed     8     2
1    		 49.4     7.8     69     2800     0.8     JESD204B     -40 to 85     8000     Yes     FCBGA | 144     144FCBGA: 100 mm2: 10 x 10 (FCBGA | 144)     Catalog     Folding Interpolating    
ADC12DJ2700 Samples not available 2700
5400    		 Ultra High Speed     12     2
1    		 57.7     9     75     2700     0.8     JESD204B     -40 to 85     8000     Yes     FCBGA | 144     144FCBGA: 100 mm2: 10 x 10 (FCBGA | 144)     Catalog     Folding Interpolating    
ADC12DJ3200 Samples not available 3200
6400    		 Ultra High Speed     12     2
1    		 57.6     9     75     3000     0.8     JESD204B     -40 to 85     8000     Yes     FCBGA | 144     144FCBGA: 100 mm2: 10 x 10 (FCBGA | 144)     Catalog     Folding Interpolating    
ADC12DL3200 Samples not available 3200
6400    		 Ultra High Speed     12     2
1    		 57.9     9     78     3150     0.8     DDR LVDS
Parallel LVDS    		 -40 to 85     8000     Yes     FCBGA | 256     256FCBGA: 289 mm2: 17 x 17 (FCBGA | 256)     Catalog     Folding Interpolating