1-A, high-PSRR, adjustable ultra-low-dropout voltage regulator with enable
Product details
Parameters
Package | Pins | Size
Features
- Low-Dropout 1-A Regulator with Enable
- Adjustable Output Voltage: 0.8 V to 6 V
- Wide-Bandwidth High PSRR:
- 80 dB at 1 kHz
- 60 dB at 100 kHz
- 54 dB at 1 MHz
- Low Noise: 23.5 µVRMS typical (100 Hz to
100 kHz) - Stable with a 4.7-µF Capacitance
- Excellent Load and Line Transient Response
- 3% Overall Accuracy (Over Load, Line,
Temperature) - Overcurrent and Overtemperature Protection
- Very Low Dropout: 170 mV Typical at 1 A
- Package: 3-mm × 3-mm SON-8
Description
The TPS7A8101 low-dropout linear regulator (LDO) offers very good performance in noise and power-supply rejection ratio (PSRR) at the output. This LDO uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.
The TPS7A8101 device is stable with a 4.7-µF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations.
This device is fully specified over the temperature range of TJ = 40°C to 125deg;C and is offered in a 3-mm × 3-mm, SON-8 package with a thermal pad.
Same functionality but is not pin-for-pin or parametrically equivalent to the compared device:
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | TPS7A8101 Low-Noise, Wide-Bandwidth, High PSRR, Low-Dropout 1-A Linear Regulator datasheet (Rev. B) | Mar. 20, 2015 |
Application note | A Topical Index of TI LDO Application Notes (Rev. F) | Jun. 27, 2019 | |
Technical articles | LDO basics: capacitor vs. capacitance | Aug. 01, 2018 | |
Technical articles | LDO Basics: Preventing reverse current | Jul. 25, 2018 | |
Selection guide | Power Management Guide 2018 (Rev. R) | Jun. 25, 2018 | |
Technical articles | LDO basics: introduction to quiescent current | Jun. 20, 2018 | |
Selection guide | Low Dropout Regulators Quick Reference Guide (Rev. P) | Mar. 21, 2018 | |
Technical articles | LDO basics: noise – part 1 | Jun. 14, 2017 | |
Application note | 4Q 2012 Issue Analog Applications Journal | Sep. 25, 2012 | |
Application note | LDO noise examined in detail | Sep. 25, 2012 | |
User guide | TPS7A8101EVM-093 Evaluation Module | Dec. 20, 2011 | |
Application note | LDO Performance Near Dropout | Oct. 08, 2010 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The ADS58J64EVM is an evaluation board used to evaluate the ADS58J64 Integrated Receiver from Texas Instruments. The ADS58J64 is a low power, 14-bit, 500-MSPS, quad channel telecom receiver with a buffered analog input. The device supports JESD204B interface and data rates up to 10Gbps. The EVM has (...)
Features
- Transformer-coupled signal input network, allows a single-ended signal source to the EVM
- On board system clock generator (LMK04828) generates the FPGA reference clock, ADC sampling clock and SYSREFs for the high-speed JESD204B serial interface
- Default transformer-coupled clock input network enables (...)
Description
The DAC38RF80EVM is the circuit board for evaluating DAC38RF80/84/90 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate. It is designed to work with the FPGA-based pattern generator card TSW14J56EVM (Rev B and up). The available (...)
Features
- Allows evaluation of DAC38RF80/84/90 up to 9-GSPS sampling rate
- Supports up to 12.5-Gbps SerDes signaling rate across FMC
- Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
- AC-coupled output with 2:1 impedance transformer for (...)
Description
Features
- Allows evaluation of DAC38RF82/83/85/93 up to 9GSPS sampling rate
- Supports up to 12.5Gbps serdes signaling rate across FMC
- Integrated low phase noise On–chip PLL with 2 VCOs to simplify system clock generation. Also supports external clock mode.
- AC coupled, differential output with on-board 2:1 (...)
Description
Features
- Allows evaluation of DAC38RF86 or DAC38RF96 up to 9-GSPS sampling rate
- Supports up to 12.5-Gbps SerDes signaling rate across FMC
- Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
- AC-coupled output with integrated impedance transformer (...)
Description
The DAC38RF89 evaluation module (EVM) is the circuit board for evaluating DAC38RF89 digital-to-analog converters (DACs). The DAC38RFEVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC (...)
Features
- Allows evaluation of DAC38RF89 up to 9-GSPS sampling rate
- Supports up to 12.5-Gbps SerDes signaling rate across FMC
- Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
- AC-coupled output with integrated impedance transformer (DAC38RF89) for (...)
Description
The DCA1000 evaluation module (EVM) provides real-time data capture and streaming for two- and four-lane low-voltage differential signaling (LVDS) traffic from TI AWR and IWR radar sensor EVMs. The data can be streamed out via 1-Gbps Ethernet in real time to a PC running the MMWAVE-STUDIO tool for (...)
Features
- Supports lab and mobile collection scenarios
- Captures LVDS data from AWR/IWR radar sensors
- Streams output in real time through 1-Gbps Ethernet
- Controlled via onboard switches or GUI/library
Description
Features
- Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz at 122.88 MHz output frequency
- Integrated Loopfilter support easy prototyping
- 0.9 W typical power consumption for 10 outputs at 122.88 MHz
- Jumper configurable supplies with on-board LDOs and DCDC converters
- GUI platform for full access (...)
Description
Features
- Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz at 122.88 MHz output frequency
- Integrated Loopfilter support easy prototyping
- 1.2 W typical power consumption for 16 outputs at 122.88 MHz
- Jumper configurable supplies with on-board LDOs and DCDC converters
- GUI platform for full access (...)
Description
The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)
Features
- Dual DPLLs with programmable bandwidths and Analog PLLs for frequency translation
- 4 clock inputs supporting hitless switching and holdover
- 8 differential or 16 LVCMOS output clocks or combination of both
- On-chip EEPROM for custom start-up clock clocks
- Flexible oscillator options: onboard XOs, TCXO, or (...)
Description
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping. SMA ports provide access to the LMK05318 clock inputs and outputs for (...)
Features
- One Digital PLL (DPLL) with programmable bandwidths and Two Fractional Analog PLLs (APLLs) for Flexible Clock Generation
- Two reference inputs to the DPLL supporting hitless switching & holdover
- Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
- On-chip EEPROM for custom start-up clock (...)
Description
Features
- Input Voltage as low as 2.2V
- 170mV dropout @ 1A
- Adjustable output from 0.8V to 6.0V
- Protections: Over current and Over temperature
- Enable pin
- Wide-Bandwidth High PSRR
- Low-Noise 3mm x 3mm SON-8 DRB Package
Design tools & simulation
Reference designs
Design files
-
download TIDA-01215 BOM.pdf (257KB) -
download TIDA-01215 Assembly Drawing.pdf (114KB) -
download TIDA-01215 PCB.pdf (2454KB) -
download TIDA-01215 CAD Files.zip (2164KB) -
download TIDA-01215 Gerber.zip (978KB)
Design files
-
download TIDA-01240 BOM.pdf (293KB) -
download TIDA-01240 Assembly Drawing.pdf (112KB) -
download TIDA-01240 PCB.pdf (2451KB) -
download TIDA-01240 CAD Files.zip (2162KB) -
download TIDA-01240 Gerber.zip (976KB)
Design files
-
download Power Optimization for 77GHz Level Transmitter Assembly Files.zip (352KB) -
download Power Optimization for 77GHz Level Transmitter Layer Plots.zip (4177KB) -
download Power Optimization for 77GHz Level Transmitter Gerber.zip (2253KB) -
download Power Optimization for 77GHz Level Transmitter Altium (Rev. A).zip (513KB) -
download Power Optimization for 77GHz Level Transmitter BOM (Rev. A).pdf (73KB) -
download Chirp Budget Calc_09_10_18.zip (52KB) -
download Chirp Budget Calc_09_25_18.zip (53KB)
Design files
-
download TIDA-010011 BOM.pdf (134KB) -
download TIDA-010011 Assembly Drawing.pdf (1564KB) -
download TIDA-010011 PCB.pdf (4603KB) -
download TIDA-010011 CAD Files.zip (7015KB) -
download TIDA-010011 Gerber.zip (799KB)
Design files
-
download TIDA-01378 BOM.pdf (301KB) -
download TIDA-01378 Assembly Files.zip (2005KB) -
download TIDA-01378 PCB.pdf (2660KB) -
download TIDA-01378 CAD Files.zip (444KB) -
download TIDA-01378 Gerber.zip (3337KB)
This (...)
Design files
-
download TIDA-01084 BOM.pdf (304KB) -
download TIDA-01084 Assembly Drawing.pdf (112KB) -
download TIDA-01084 PCB.pdf (2451KB) -
download TIDA-01084 CAD Files.zip (2162KB) -
download TIDA-01084 Gerber.zip (976KB)
Design files
-
download TIDA-00630 BOM.pdf (231KB) -
download TIDA-00630 Assembly Drawing.pdf (737KB) -
download TIDA-00630 PCB.pdf (4256KB) -
download TIDA-00630 Gerber.zip (971KB)
Design files
-
download TIDA-00294 BOM.pdf (87KB) -
download TIDA-00294 PCB.pdf (3003KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SON (DRB) | 8 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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