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Product details

Parameters

Output options Adjustable Output Iout (Max) (A) 1 Vin (Max) (V) 6.5 Vin (Min) (V) 2.2 Vout (Max) (V) 6 Vout (Min) (V) 0.8 Noise (uVrms) 23 Iq (Typ) (mA) 0.06 Thermal resistance θJA (°C/W) 48 Load capacitance (Min) (µF) 4.7 Rating Catalog Regulated outputs (#) 1 Features Enable Accuracy (%) 3 PSRR @ 100 KHz (dB) 60 Dropout voltage (Vdo) (Typ) (mV) 170 Operating temperature range (C) -40 to 125 open-in-new Find other Linear regulators (LDO)

Package | Pins | Size

VSON (DRB) 8 9 mm² 3 x 3 open-in-new Find other Linear regulators (LDO)

Features

  • Low-Dropout 1-A Regulator with Enable
  • Adjustable Output Voltage: 0.8 V to 6 V
  • Wide-Bandwidth High PSRR:
    • 80 dB at 1 kHz
    • 60 dB at 100 kHz
    • 54 dB at 1 MHz
  • Low Noise: 23.5 µVRMS typical (100 Hz to
    100 kHz)
  • Stable with a 4.7-µF Capacitance
  • Excellent Load and Line Transient Response
  • 3% Overall Accuracy (Over Load, Line,
    Temperature)
  • Overcurrent and Overtemperature Protection
  • Very Low Dropout: 170 mV Typical at 1 A
  • Package: 3-mm × 3-mm SON-8
open-in-new Find other Linear regulators (LDO)

Description

The TPS7A8101 low-dropout linear regulator (LDO) offers very good performance in noise and power-supply rejection ratio (PSRR) at the output. This LDO uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.

The TPS7A8101 device is stable with a 4.7-µF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations.

This device is fully specified over the temperature range of TJ = –40°C to 125&#deg;C and is offered in a 3-mm × 3-mm, SON-8 package with a thermal pad.

open-in-new Find other Linear regulators (LDO)
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Similar products you might be interested in
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Same functionality but is not pin-for-pin or parametrically equivalent to the compared device:
TPS7A91 ACTIVE 1-A, low-noise, high-PSRR, adjustable ultra-low-dropout voltage regulator with high-accuracy 1-A, low noise (4.7uVrms) LDO in a small package (2.5 mm x 2.5mm)
Similar but not functionally equivalent to the compared device:
TPS7A88 ACTIVE 1-A, low-noise, high-PSRR, dual-channel adjustable ultra-low-dropout voltage regulator TPS7A88 is a dual-channel, low noise, 1-A LDO.

Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet TPS7A8101 Low-Noise, Wide-Bandwidth, High PSRR, Low-Dropout 1-A Linear Regulator datasheet (Rev. B) Mar. 20, 2015
Application note A Topical Index of TI LDO Application Notes (Rev. F) Jun. 27, 2019
Technical articles LDO basics: capacitor vs. capacitance Aug. 01, 2018
Technical articles LDO Basics: Preventing reverse current Jul. 25, 2018
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
Technical articles LDO basics: introduction to quiescent current Jun. 20, 2018
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) Mar. 21, 2018
Technical articles LDO basics: noise – part 1 Jun. 14, 2017
Application note 4Q 2012 Issue Analog Applications Journal Sep. 25, 2012
Application note LDO noise examined in detail Sep. 25, 2012
User guide TPS7A8101EVM-093 Evaluation Module Dec. 20, 2011
Application note LDO Performance Near Dropout Oct. 08, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The ADS58J64EVM is an evaluation board used to evaluate the ADS58J64 Integrated Receiver from Texas Instruments. The ADS58J64 is a low power, 14-bit, 500-MSPS, quad channel telecom receiver with a buffered analog input. The device supports JESD204B interface and data rates up to 10Gbps. The EVM has (...)

Features
  • Transformer-coupled signal input network, allows a single-ended signal source to the EVM
  • On board system clock generator (LMK04828) generates the FPGA reference clock, ADC sampling clock and SYSREFs for the high-speed JESD204B serial interface
  • Default transformer-coupled clock input network enables (...)
EVALUATION BOARD Download
Description

The DAC38RF80EVM is the circuit board for evaluating DAC38RF80/84/90 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate. It is designed to work with the FPGA-based pattern generator card TSW14J56EVM (Rev B and up). The available (...)

Features
  • Allows evaluation of DAC38RF80/84/90 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with 2:1 impedance transformer for (...)
EVALUATION BOARD Download
Description
The DAC38RF82EVM is the circuit board for evaluating DAC38RF82/83/85/93 digital to analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9GSPS sampling rate and it is designed to work with the TSW14J56 EVM. The available FMC connector also makes it possible to (...)
Features
  • Allows evaluation of DAC38RF82/83/85/93 up to 9GSPS sampling rate
  • Supports up to 12.5Gbps serdes signaling rate across FMC
  • Integrated low phase noise On–chip PLL with 2 VCOs to simplify system clock generation. Also supports external clock mode.
  • AC coupled, differential output with on-board 2:1 (...)
EVALUATION BOARD Download
Description
The DAC38RF86 evaluation module (EVM) is the circuit board for evaluating DAC38RF86 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC connector also (...)
Features
  • Allows evaluation of DAC38RF86 or DAC38RF96 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (...)
EVALUATION BOARD Download
Description

The DAC38RF89 evaluation module (EVM) is the circuit board for evaluating DAC38RF89 digital-to-analog converters (DACs). The DAC38RFEVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate and is designed to work with the TSW14J56EVM (Rev B and up). The available FMC (...)

Features
  • Allows evaluation of DAC38RF89 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with integrated impedance transformer (DAC38RF89) for (...)
EVALUATION BOARD Download
499
Description

The DCA1000 evaluation module (EVM) provides real-time data capture and streaming for two- and four-lane low-voltage differential signaling (LVDS) traffic from TI AWR and IWR radar sensor EVMs. The data can be streamed out via 1-Gbps Ethernet in real time to a PC running the MMWAVE-STUDIO tool for (...)

Features
  • Supports lab and mobile collection scenarios
  • Captures LVDS data from AWR/IWR radar sensors
  • Streams output in real time through 1-Gbps Ethernet
  • Controlled via onboard switches or GUI/library
EVALUATION BOARD Download
399
Description
The LMK04610EVM features LMK04610 ultra Low-noise and low power JESD204B compliant Dual Loop Jitter Cleaner. With a power consumption of only 900 mW with all outputs running, LMK04610 supports sub-74 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. Integrated LDOs provide high PSRR that (...)
Features
  • Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz  at 122.88 MHz output frequency
  • Integrated Loopfilter support easy prototyping
  • 0.9 W typical power consumption for 10 outputs at 122.88 MHz
  • Jumper configurable supplies with on-board LDOs and DCDC converters
  • GUI platform for full access (...)
EVALUATION BOARD Download
499
Description
The LMK04616EVM features LMK04616 ultra Low-noise and low power JESD204B compliant Dual Loop Jitter Cleaner. With a power consumption of only 1200 mW with 16 outputs running, LMK04616 supports 65 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. Integrated LDOs provide high PSRR that (...)
Features
  • Dual Loop Architecture with typical 60 fs rms from 10 kHz to 20 MHz at 122.88 MHz output frequency
  • Integrated Loopfilter support easy prototyping
  • 1.2 W typical power consumption for 16 outputs at 122.88 MHz
  • Jumper configurable supplies with on-board LDOs and DCDC converters
  • GUI platform for full access (...)
EVALUATION BOARD Download
399
Description

The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)

Features
  • Dual DPLLs with programmable bandwidths and Analog PLLs for frequency translation
  • 4 clock inputs supporting hitless switching and holdover
  • 8 differential or 16 LVCMOS output clocks or combination of both 
  • On-chip EEPROM for custom start-up clock clocks
  • Flexible oscillator options: onboard XOs, TCXO, or (...)
EVALUATION BOARD Download
399
Description
The LMK05318EVM is an evaluation module for the LMK05318 Network Synchronizer Clock device.
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping.  SMA ports provide access to the LMK05318 clock inputs and outputs for (...)
Features
  • One Digital PLL (DPLL) with programmable bandwidths and Two Fractional Analog PLLs (APLLs) for Flexible Clock Generation
  • Two reference inputs to the DPLL supporting hitless switching & holdover
  • Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
  • On-chip EEPROM for custom start-up clock (...)
EVALUATION BOARD Download
20
Description
The TPS7A8101EVM-093 evaluation module (EVM) helps you evaluate the performance of the TPS7A8101 low-noise, wide-bandwidth, high-PSRR, low-dropout 1-A linear regulator with enable. The EVM is a stand alone evaluation module containing a low-dropout regulator IC for adjustable voltage regulation (...)
Features
  • Input Voltage as low as 2.2V
  • 170mV dropout @ 1A
  • Adjustable output from 0.8V to 6.0V
  • Protections: Over current and Over temperature
  • Enable pin
  • Wide-Bandwidth High PSRR
  • Low-Noise 3mm x 3mm SON-8 DRB Package

Design tools & simulation

SIMULATION MODEL Download
SBVM110.ZIP (33 KB) - PSpice Model
GERBER FILE Download
SLVC403.ZIP (236 KB)

Reference designs

REFERENCE DESIGNS Download
Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs
TIDA-01215 — This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)
document-generic Schematic
REFERENCE DESIGNS Download
RF-Sampling S-Band Radar Transmitter Reference Design
TIDA-01240 — Synthesis of waveforms appropriate for an S-band multifunction phased array radar (MPAR) is demonstrated with an RF sampling architecture utilizing the DAC38RF80, a 9GSPS 16-bit digital-to-analog converter (DAC). The RF sampling transmit architecture simplifies the signal chain, bringing the data (...)
document-generic Schematic
REFERENCE DESIGNS Download
Power optimization for 77GHz-level transmitter reference design
TIDEP-0091 TI Design TIDEP-0091 highlights strategies for power optimization of IWR14xx 76- to 81-GHz mmWave sensors in tank level-probing applications, displacement sensors, 4- to 20-mA sensors, and other low-power applications for detecting range with high accuracy in a minimal power envelope. In these (...)
document-generic Schematic
REFERENCE DESIGNS Download
High efficiency power supply architecture reference design for protection relay processor module
TIDA-010011 — This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
document-generic Schematic
REFERENCE DESIGNS Download
Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications
TIDA-01378 — This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)
document-generic Schematic
REFERENCE DESIGNS Download
Continuous Wave Phase-aligned Multitone Generator: DC-to-6-GHz RF-Sampling DAC Reference Design
TIDA-01084 The TIDA-01084 reference design demonstrates the use of RF sampling DAC to generate continuous phase-aligned multitone waveforms. With four 48-bit independent NCOs, the 14-bit, 9GSPS DAC38RF83 can generate four CW tones placed anywhere within the first Nyquist zone or up to 6 GHz in the second.

This (...)

document-generic Schematic
REFERENCE DESIGNS Download
TI USB Type-C Dock Reference Design
TIDA-00630 The Type-C Dock Board is designed to help evaluate Type-C Dock implementations with video and charging support.  The Type-C Dock offers data and video port expansion and a charging capability for Type-C systems that support USB PD/Alternate mode protocol.  The dock comes with three (...)
document-generic Schematic
REFERENCE DESIGNS Download
High Perf Single Ended to Diff Active Interface for High Speed ADC Developed by Dallas Logic Corp
Provided by Dallas Logic Corporation This reference design uses the ADC34J22 12b 50Msps JESD204B data converter and the THS4541 fully differential amplifer to demonstrate how to design a high performance active interface for high speed ADCs.  This type of circuit can be used in sensor front end, motor control, and test and (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SON (DRB) 8 View options

Ordering & quality

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