2-port 100GbE/40GbE/10GbE QSFP28 Signal Conditioner Reference Design


Design files


This verified reference design is a signal conditioning solution for front-port QSFP28 supporting two 100GbE ports compatible with 100G-CR4/SR4/LR4, 40G-CR4/SR4/LR4 and 10G SFF-8431 requirements. The design is applicable to optical and passive/active copper cables. It allows for reach extension between the Switch ASIC and the front-port QSFP28 which is often required for the outermost ports of a Top-of-Rack (ToR) switch or for add-in mezzanine implementations of QSFP28 line cards. This reference design offers the flexibility for users to upgrade from a DS280BR810 Repeater to the pin-compatible DS250DF810 Retimer.

  • Front-port stacked QSFP28 implementation with signal conditioning to support 100GbE/40GbE/10GbE optical and passive copper
  • Extends reach between Switch and front-port by up to 3x beyond CAUI-4 host channel loss limit
  • Low-power/low-cost solution for front-port signal conditioning
  • Applicable to Top-of-Rack (ToR) switch and line card systems
  • Single power supply, no firmware required, no heatsink required, no reference clock required
  • Lab-tested HW example including 100GbE/40GbE/10GbE-specific test data

A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUBG6.PDF (4696 K)

Reference design overview and verified performance test data

TIDUBF8.PDF (1859 K)

Test results for the reference design, including efficiency graphs, test prerequisites and more

TIDRK65.PDF (207 K)

Detailed schematic diagram for design layout and components

TIDRK66.PDF (115 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRK67.ZIP (1885 K)

Detailed overview of design layout for component placement

TIDRK68.PDF (447 K)

Detailed overview of design layout for component placement

TIDRK70.ZIP (2370 K)

Files used for 3D models or 2D drawings of IC components

TIDCBQ7.ZIP (2204 K)

Design file that contains information on physical board layer of design PCB

TIDRK69.PDF (4178 K)

PCB layer plot file used for generating PCB design layout


Includes TI products in the design and potential alternatives.

Ethernet retimers, redrivers & mux-buffers

DS250DF81025-Gbps multi-rate 8-channel retimer

Data sheet: PDF | HTML
Ethernet retimers, redrivers & mux-buffers

DS280BR81028-Gbps low power 8-channel linear redriver

Data sheet: PDF | HTML
Ethernet retimers, redrivers & mux-buffers

DS280BR82028-Gbps low power 8-channel redriver

Data sheet: PDF | HTML
Ethernet retimers, redrivers & mux-buffers

DS280DF81028-Gbps multi-rate 8-channel retimer

Data sheet: PDF
Ethernet retimers, redrivers & mux-buffers

DS280MB81028-Gbps low power 8 channel redriver with crosspoint

Data sheet: PDF | HTML
ESD & surge protection ICs

TPD4E004Quad 0.8-pF, 5.5-V, ±8-kV ESD protection diode with with VCC pin for High Speed Interfaces

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS735500-mA, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
MSP430 microcontrollers

MSP430F552925 MHz MCU with 128KB Flash, 8KB SRAM, 12-bit ADC, comparator, DMA, UART/SPI/I2C, USB, HW multiplier

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide Two-Port 40- and 100-GbE QSFP28 Signal Conditioner Reference Design Guide Jan. 28, 2016
* Test report TIDA-00427 DS280BR810 100G QSFP28 Test Setup Jan. 22, 2016

Related design resources

Reference designs

TIDA-00417 2-port 40GbE/10GbE QSFP+ Signal Conditioner Reference Design

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