The DS250DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.
Each channel of the DS250DF810 independently locks to serial data rates in a continuous range from 20.6 Gbps to 25.8 Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.3125 Gbps and 12.5 Gbps, which allows the DS250DF810 to support individual lane Forward Error Correction (FEC) pass-through.
Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS250DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost.
The advanced equalization features of the DS250DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is ideal for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. The DS250DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options.
The DS250DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator/checker allow for in-system diagnostics.
The IBIS AMI models, device programming guide and device GUI profile, are available. Request now
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS250DF810 25 Gbps Multi-Rate 8-Channel Retimer datasheet (Rev. C) | PDF | HTML | Oct 24, 2019 |
| Application note | Implementing Pin Compatible Ethernet Redrivers and Retimers | PDF | HTML | Oct 28, 2024 | |
| Application note | Optimal Implementation of 25G-28G Ethernet Retimers versus Redrivers (Rev. B) | PDF | HTML | May 1, 2023 | |
| Application note | DS2X0DF810 Junction Temperature Readback and Temperature Lock Range (TLR) Extens | PDF | HTML | May 24, 2021 | |
| Application note | Transmitter Optimization for ≥ 25Gbps Retimer Links | Sep 8, 2017 | ||
| More literature | Advanced Signal Conditioning Made Easy and Efficient | Jan 12, 2017 | ||
| Analog design Journal | Green box testing: A method for optimizing high-speed serial links | Jul 21, 2016 | ||
| Technical article | Designing a 25G system: 5 tips to balance power, performance and price | PDF | HTML | Feb 1, 2016 | |
| Application note | Understanding EEPROM Programming for 25G and 28G Repeaters and Retimers | PDF | HTML | Jan 13, 2016 |
For additional terms or required resources, click any title below to view the detail page where available.
The DS250DF810EVM allows for easy evaluation of the 25 Gbps retimer DS250DF810. Users are required to supply power and high speed traffic to the EVM via Huber+Suhner 1x8 MXP connectors. Huber+Suhner cables are not included.
Through the onboard USB2ANY connection and EVM software, users can evaluate (...)
This verified reference design is a signal conditioning solution for front-port QSFP28 supporting two 100GbE ports compatible with 100G-CR4/SR4/LR4, 40G-CR4/SR4/LR4 and 10G SFF-8431 requirements. The design is applicable to optical and passive/active copper cables. It allows for reach extension (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCCSP (ABV) | 135 | Ultra Librarian |
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