Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
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A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the
sampled data from the ADCs are phase aligned.

  • Synchronized 2 giga sample ADCs sampling at 3.072GHz
  • System expandable to more than 2 ADCs
  • Phase variation less than 1 ADC clock period
  • Easy to use software interface for control and data acquisition
  • Excellent spur and noise perfromance of ADC at 3.072GHz
  • This design is tested and includes software, demo hardware and a design guide.

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Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps


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TI Devices (2)

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Part Number Name Product Family Sample & Buy Design Kits & Evaluation Modules
ADC12J4000  12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)  Analog-to-digital converters (ADCs)  Sample & Buy View Design Kits & Evaluation Modules
LMK04828  Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.  Clocks & timing  Sample & Buy View Design Kits & Evaluation Modules

CAD/CAE symbols

Part # Package | Pins CAD File (.bxl) STEP Model (.stp)
ADC12J4000 Download Download
LMK04828 Download Download

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Technical documentation

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User guide (1)
Title Type Size (KB) Date
PDF 603 24 Mar 2015
Selection guide (1)
Title Type Size (KB) Date
PDF 9699 22 Mar 2017
Design files (10)
Title Type Size (KB) Date
ZIP 1436 13 Apr 2015
ZIP 712 13 Apr 2015
ZIP 9933 13 Apr 2015
PDF 2955 13 Apr 2015
PDF 117 13 Apr 2015
PDF 1261 13 Apr 2015
PDF 216 13 Apr 2015
PDF 318 13 Apr 2015
PDF 250 13 Apr 2015
PDF 1278 13 Apr 2015
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Software development (1)

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