ADC12J4000

VQFNP (NKE)

100 mm² 10 x 10

Excellent Noise and Linearity up to and beyond F_IN = 3 GHz
Configurable DDC
Decimation Factors from 4 to 32 (Complex Baseband Out)
Usable Output Bandwidth of 800 MHz at
4x Decimation and 4000 MSPS
Usable Output Bandwidth of 100 MHz at
32x Decimation and 4000 MSPS
Bypass Mode for Full Nyquist Output Bandwidth
Low Pin-Count JESD204B Subclass 1 Interface
Automatically Optimized Output Lane Count
Embedded Low Latency Signal Range Indication
Low Power Consumption
Key Specifications:
- Max Sampling Rate: 4000 MSPS
- Min Sampling Rate: 1000 MSPS
- DDC Output Word Size: 15-Bit Complex (30 bits total)
- Bypass Output Word Size: 12-Bit Offset Binary
- Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz
- IMD3: −64 dBc (F_IN = 2140 MHz ± 30 MHz at −13 dBFS)
- FPBW (–3 dB): 3.2 GHz
- Peak NPR: 46 dB
- Supply Voltages: 1.9 V and 1.2 V
- Power Consumption
  - Bypass (4000 MSPS): 2 W
  - Decimate by 10 (4000 MSPS): 2 W
  - Power Down Mode: <50 mW

Excellent Noise and Linearity up to and beyond F_IN = 3 GHz
Configurable DDC
Decimation Factors from 4 to 32 (Complex Baseband Out)
Usable Output Bandwidth of 800 MHz at
4x Decimation and 4000 MSPS
Usable Output Bandwidth of 100 MHz at
32x Decimation and 4000 MSPS
Bypass Mode for Full Nyquist Output Bandwidth
Low Pin-Count JESD204B Subclass 1 Interface
Automatically Optimized Output Lane Count
Embedded Low Latency Signal Range Indication
Low Power Consumption
Key Specifications:
- Max Sampling Rate: 4000 MSPS
- Min Sampling Rate: 1000 MSPS
- DDC Output Word Size: 15-Bit Complex (30 bits total)
- Bypass Output Word Size: 12-Bit Offset Binary
- Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz
- IMD3: −64 dBc (F_IN = 2140 MHz ± 30 MHz at −13 dBFS)
- FPBW (–3 dB): 3.2 GHz
- Peak NPR: 46 dB
- Supply Voltages: 1.9 V and 1.2 V
- Power Consumption
  - Bypass (4000 MSPS): 2 W
  - Decimate by 10 (4000 MSPS): 2 W
  - Power Down Mode: <50 mW

The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ T_A ≤ 85°C) ambient temperature range.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ T_A ≤ 85°C) ambient temperature range.

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Technical documentation

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	Type	Title	Date
*	Data sheet	ADC12J4000 12-Bit, 4-GSPS ADC With Integrated DDC datasheet (Rev. D)	19 Oct 2017
	Technical article	Keys to quick success using high-speed data converters	13 Oct 2020
	Technical article	How to achieve fast frequency hopping	03 Mar 2019
	Technical article	RF sampling: Learning more about latency	09 Feb 2017
	Technical article	Why phase noise matters in RF sampling converters	28 Nov 2016
	Application note	66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B)	20 Jun 2016
	Design guide	66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A)	22 Oct 2015
	User guide	TSW12J54EVM User's Guide	21 Oct 2015
	Application note	System solution for avionics & defense	23 Sep 2015
	User guide	ADC12J4000EVM User's Guide (Rev. B)	27 Jul 2015
	Analog design journal	Analog Applications Journal 2Q 2015	28 Apr 2015
	Analog design journal	JESD204B multi-device synchronization: Breaking down the requirements	28 Apr 2015
	White paper	Ready to make the jump to JESD204B? White Paper (Rev. B)	19 Mar 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12J4000EVM — ADC12J4000 12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter Evaluation Module

The ADC12J4000EVM is an evaluation module (EVM) that allows for the evaluation of TI's ADC12J4000. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and decimation (...)

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User guide

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Evaluation board

TSW12J54EVM — Wideband RF receiver reference design

RF Sampling 4GSPS ADC with 8GHz DC-Coupled Fully differential Amplifier. Provides a wide bandwidth high performance AC- or DC-coupled capture platform with up to 2 GHz of continous capture bandwidth. Built-in DDC functions enable tuning, down-conversion and bandwidth reduction of captured signals (...)

User guide

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Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)

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Simulation model

ADC12J4000 IBIS-AMI Model (Rev. A)

SLAM198A.ZIP (4134 KB) - IBIS-AMI Model

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Simulation model

ADC12J1600 IBIS Model (Rev. A)

SLAM223A.ZIP (24 KB) - IBIS Model

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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

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Calculation tool

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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Reference designs

TIDA-00431 — RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier

Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

Reference designs

TIDA-01017 — High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars

The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)

Reference designs

TIDA-01015 — 4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers

The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input (...)

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TIDEP0034 — 66AK2L06 DSP+ARM Processor with JESD204B Attach to Wideband ADCs and DACs

For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)

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TIDA-00826 — 50-Ohm 2-GHz Oscilloscope Front-end Reference Design

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.

Reference designs

TIDA-00467 — Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design

A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual (...)

Reference designs

TIDA-00432 — Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)