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ADC12J4000

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12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

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12-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

ADC12J4000

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Product details

Parameters

Sample rate (Max) (MSPS) 4000 Resolution (Bits) 12 Number of input channels 1 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.725 Power consumption (Typ) (mW) 2000 Architecture Folding Interpolating SNR (dB) 55 ENOB (Bits) 8.8 SFDR (dB) 71 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFNP (NKE) 68 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Excellent Noise and Linearity up to and beyond FIN = 3 GHz
  • Configurable DDC
  • Decimation Factors from 4 to 32 (Complex Baseband Out)
  • Usable Output Bandwidth of 800 MHz at
    4x Decimation and 4000 MSPS
  • Usable Output Bandwidth of 100 MHz at
    32x Decimation and 4000 MSPS
  • Bypass Mode for Full Nyquist Output Bandwidth
  • Low Pin-Count JESD204B Subclass 1 Interface
  • Automatically Optimized Output Lane Count
  • Embedded Low Latency Signal Range Indication
  • Low Power Consumption
  • Key Specifications:
    • Max Sampling Rate: 4000 MSPS
    • Min Sampling Rate: 1000 MSPS
    • DDC Output Word Size: 15-Bit Complex (30 bits total)
    • Bypass Output Word Size: 12-Bit Offset Binary
    • Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz
    • IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS)
    • FPBW (–3 dB): 3.2 GHz
    • Peak NPR: 46 dB
    • Supply Voltages: 1.9 V and 1.2 V
    • Power Consumption
      • Bypass (4000 MSPS): 2 W
      • Decimate by 10 (4000 MSPS): 2 W
      • Power Down Mode: <50 mW

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments’ giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF. An integrated DDC (Digital Down Converter) provides digital filtering and down-conversion. The selected frequency block is made available on a JESD204B serial interface. Data is output as baseband 15-bit complex information for ease of downstream processing. Based on the digital down-converter (DDC) decimation and link output rate settings, this data is output on 1 to 5 lanes of the serial interface.

A DDC bypass mode allows the full rate 12-bit raw ADC data to also be output. This mode of operation requires 8 lanes of serial output.

The ADC12J4000 device is available in a 68-pin VQFN package. The device operates over the Industrial (–40°C ≤ TA ≤ 85°C) ambient temperature range.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 13
Type Title Date
* Datasheet ADC12J4000 12-Bit, 4-GSPS ADC With Integrated DDC datasheet (Rev. D) Oct. 19, 2017
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) Jun. 20, 2016
User guide 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) Oct. 22, 2015
User guide TSW12J54EVM User's Guide Oct. 21, 2015
Application note System solution for avionics & defense Sep. 23, 2015
User guide ADC12J4000EVM User's Guide (Rev. B) Jul. 27, 2015
Application note Analog Applications Journal 2Q 2015 Apr. 28, 2015
Application note JESD204B multi-device synchronization: Breaking down the requirements Apr. 28, 2015
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) Mar. 19, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
Description

The ADC12J4000EVM is an evaluation module (EVM) that allows for the evaluation of TI's ADC12J4000. The ADC12J4000 is a low power, 12-bit, 4-GSPS RF-sampling analog to digital converter (ADC) with a buffered analog input, integrated Digital Down Converter with programmable NCO and decimation settings (...)

Features
  • Flexible transformer coupled analog input and clock input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADC12J4000, LMX2581 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data (...)
View details
EVALUATION BOARD Download
document-generic User guide
1999
Description

RF Sampling 4GSPS ADC with 8GHz DC-Coupled Fully differential Amplifier. Provides a wide bandwidth high performance AC- or DC-coupled capture platform with up to 2 GHz of continous capture bandwidth. Built-in DDC functions enable tuning, down-conversion and bandwidth reduction of captured signals (...)

Features

  • 12-bit 4GSPS ADC - ADC12J4000
  • 8GHz Fully Differential Amplifier - LMH5401
  • 4.8 GHz Low Phase Noise PLL/VCO TRF3765
  • Clock Jitter Cleaner LMK04828
  • Complete TI Power Solution
  • 2GHz Butterworth Low Pass Filter Design

View details

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP — The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
View details
SUPPORT SOFTWARE Download
High-speed data converter pro software
DATACONVERTERPRO-SW — This high-speed data converter pro GUI is a PC (Windows® XP/7 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Features
  • Compatible with TSW1400, TSW1405, TSW1406 and TSW14J10, TSW14J50, TSW14J56, and TSW14J57 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)
View details

Design tools & simulation

SIMULATION MODEL Download
SLAM198A.ZIP (4134 KB) - IBIS-AMI Model
SIMULATION MODEL Download
SLAM223A.ZIP (24 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
View details
CALCULATION TOOL Download
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC — This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)
Features
  • Frequency planning
  • Analog filtering
  • Decimation filter spur location
View details

Reference designs

REFERENCE DESIGNS Download
Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
TIDA-00467 — A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
TIDA-00431 — Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars
TIDA-01017 — The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers
TIDA-01015 — The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input bandwidth (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
66AK2L06 DSP+ARM Processor with JESD204B Attach to Wideband ADCs and DACs
TIDEP0034 — For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
50-Ohm 2-GHz Oscilloscope Front-end Reference Design
TIDA-00826 — This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
TIDA-00432 — This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Clocking Solution Reference Design for GSPS ADCs
TIDA-00359 — Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (NKE) 68 View options

Ordering & quality

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