This reference design describes system considerations for Dual Data Rate (DDR) memory interface with Error Correcting Code (ECC) support in high-reliability applications, based on the 66AK2Gx Multicore DSP + ARM processor System-on-Chip (SoC). It enables developers to implement a high reliability based solution rapidly by discussing system interfaces, board hardware, software, throughput performance and diagnostic procedures.
- Optimized high speed signal routing
- Surface-mount PCIe x1 socket
- Example of AC coupling capacitor placement
- Example of recommended differential pair spacing