Wideband Dual Receiver Reference Design and Evaluation Platform


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The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL clock jitter cleaner and generator to provide an onboard low-noise clocking solution. A software GUI is provided to allow for configuration of the ADS4249 and LMK04800. The gain of the LMH6521 DVGA can be controlled through the GUI or alternatively through the high speed connector with an FPGA. The EVM is designed to mate with the TSW1400EVM pattern capture and generation board to capture data from the ADS4249. Signal analysis can then be performed with the High Speed Data Converter Pro software tool.

  • Complete RF-to-bits receiver evaluation platform utilizing a dual-channel downconverter, LMH6521 DVGA, and ADS4249 14-bit 250-MSPS ADC
  • The LMK04800 clock generator and jitter-cleaning provides a complete onboard clocking solution
  • A software GUI is provided to configure the ADS4249, LMK04800, and LMH6521
  • Easily interfaces with the TSW1400 pattern capture and generation card for quick evaluation
  • High-speed ADCs (>10MSPS)
    ADS4249 Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC)


    Clock jitter cleaners & synchronizers
    LMK04803 Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO LMK04805 Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.2-GHz VCO LMK04806 Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO


    RF VGAs
    LMH6521 High Performance Dual DVGA

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    Evaluation board

    TSW1265EVM — TSW1265 Wideband dual receiver reference design and evaluation platform

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    GUI for evaluation module (EVM)

    TSW1265 GUI Software Installer — SLWC105.ZIP (121403KB)

    TI's Standard Terms and Conditions for Evaluation Items apply.

    Design files

    Technical documentation

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    Type Title Date
    Certificate TSW1265EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
    User guide TSW1265 User's Guide Mar. 14, 2012

    Related design resources

    Hardware development

    TSW1400EVM Data Capture/Pattern Generator: Data Converter Evaluation Module With 8 LVDS Lanes up to 1.5Gbps

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