Product details

Sample rate (Max) (MSPS) 250 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 600 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 470 Architecture Pipeline SNR (dB) 72.8 ENOB (Bits) 11.45 SFDR (dB) 82 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 250 Resolution (Bits) 14 Number of input channels 2 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 600 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 470 Architecture Pipeline SNR (dB) 72.8 ENOB (Bits) 11.45 SFDR (dB) 82 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 250 MSPS
  • Ultra-Low Power with Single 1.8-V Supply:
    • 560-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80-dBc SFDR at 170 MHz
    • 71.7-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with
      Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
    Lead (QFN) Package
  • Maximum Sample Rate: 250 MSPS
  • Ultra-Low Power with Single 1.8-V Supply:
    • 560-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80-dBc SFDR at 170 MHz
    • 71.7-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain up to 6 dB for
    SNR/SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • Double Data Rate (DDR) LVDS with
      Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
    Lead (QFN) Package

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact QFN-64 PowerPAD package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).

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Technical documentation

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Type Title Date
* Data sheet ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC datasheet (Rev. E) 07 Jan 2016
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Signal Chain Noise Figure Analysis 29 Oct 2014
Design guide TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide 03 Sep 2013
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide ADS42xx EVM User’s Guide (Rev. A) 21 Jun 2013
User guide TIDA-00070 Verified Design Reference Guide 23 Jan 2013
User guide HSDC-SEK-10 17 Jan 2013
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 Jul 2012
Application note High-Speed, Analog-to-Digital Converter Basics 11 Jan 2012
User guide TSW3725 Evaluation Module 25 Oct 2011
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS4249EVM — ADS4249 Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter Evaluation Module

The ADS4249EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4249 device, an extremely low power dual channel 14-bit 250 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a (...)

Out of stock on TI.com
Evaluation board

TSW1265EVM — Wideband Dual Receiver Reference Design and Evaluation Platform

The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)

In stock
Limit: 3
Evaluation board

TSW1405EVM — Data converter data capture evaluation module with 8 LVDS lanes up to 1.0 Gbps

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample depth (...)

In stock
Limit: 3
GUI for evaluation module (EVM)

ADS42xxx SPI GUI (Rev. B)

SBAC113B.ZIP (129504 KB)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Simulation model

ADS4249 IBIS Model

SBAM107.ZIP (41 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Schematic

ADS42XX_58C28EVM DesignPkg (Rev. B)

SLAC459B.ZIP (6548 KB)
Reference designs

TIDA-00073 — Dual-Wideband RF-to-Digital Receiver Design

The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this.  This reference EVEM coupled with a capture card (...)
Reference designs

TIDA-00070 — FPGA Firmware Project for Measuring Bit Errors in the Output Word of an A to D Converter

For applications where there are bit errors and resulting sample errors (also called sparkle codes, word errors, or code errors), the ability to measure the Error rates caused by these bit errors is important. This FPGA firmware based application note proposes a method to accurately measure these (...)
Reference designs

TIDA-00069 — FPGA Firmware Example of How To Interface Altera FPGAs to High-Speed LVDS-Interface Data Converters

This reference design and the associated example Verilog code can be used as a starting point for interfacing Altera FPGAs to Texas Instruments' high-speed LVDS-interface analog-to-digital converters (ADC) and digital-to-analog converters (DAC). The firmware implementation is explained and the (...)
Reference designs

TIDA-00068 — Basestation Transceiver with DPD Feedback Path

The design is for a small cell base station development platform.  It provides two real receive paths, two complex transmit paths, and a shared real feedback path.  This design has macro basestation performance, but with small cell base station footprint.  The current design handles (...)
Package Pins Download
VQFN (RGC) 64 View options

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