LMK04808

ACTIVE

Low-Noise Clock Jitter Cleaner with Dual Loop PLLs and Integrated 2.9 GHz VCO

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Product details

Parameters

Function Dual-loop PLL Number of outputs 14 Number of Inputs 2 RMS jitter (fs) 111 Output frequency (Min) (MHz) 0.22 Output frequency (Max) (MHz) 3072 Input type LVCMOS, LVDS, LVPECL Output type LVCMOS, LVDS, LVPECL Supply voltage (Min) (V) 3.15 Supply voltage (Max) (V) 3.45 Features 0 Delay Operating temperature range (C) -40 to 85 open-in-new Find other Clock jitter cleaners & synchronizers

Package | Pins | Size

WQFN (NKD) 64 81 mm² 9 x 9 open-in-new Find other Clock jitter cleaners & synchronizers

Features

  • Ultra-Low RMS Jitter Performance
    • 111 fs RMS Jitter (12 kHz to 20 MHz)
    • 123 fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Integrated Low-Noise Crystal Oscillator
      Circuit
    • Holdover Mode when Input Clocks are Lost
    • Automatic or Manual Triggering/Recovery
  • PLL2
    • Normalized PLL Noise Floor of –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Integrated Low-Noise VCO
  • 2 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50 % Duty Cycle Output Divides, 1 to 1045 (Even
    and Odd)
  • 12 LVPECL, LVDS, or LVCMOS Programmable
    Outputs
  • Digital Delay: Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control.
  • 14 Differential Outputs. Up to 26 Single Ended.
    • Up to 6 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 1536 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-Mode: Dual PLL, Single PLL, and Clock
    Distribution
  • Industrial Temperature Range: –40 to 85°C
  • 3.15-V to 3.45-V Operation
  • 2 Dedicated Buffered/Divided OSCin Clocks
  • Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
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Description

The LMK0480x family is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

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Similar but not functionally equivalent to the compared device:
LMK04821 ACTIVE Ultra Low Jitter Synthesizer and Jitter Cleaner with JESD204B Support LMK04821( it has additional features and better performance)

Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) Dec. 24, 2014
User guide TSW308x Evaluation Module (Rev. B) May 18, 2016
User guide TSW4806EVM User's Guide (Rev. A) Apr. 26, 2016
User guide LMK0480x Evaluation Board Instructions (Rev. B) Aug. 04, 2014
Technical articles Increasing dynamic performance in radar systems May 10, 2014
User guide TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide Sep. 03, 2013
Application note Using the LMK0480x/LMK04906 for Hitless Switching and Holdover Jul. 12, 2013
Application note Effects of Clock Noise on High Speed DAC Performance Nov. 08, 2012
User guide TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) Dec. 29, 2011
User guide Clock Conditioner Owner's Manual Nov. 10, 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The DAC34SH84EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' four-channel, ultra-low power, 16-bit, 1.5 GSPS DAC34SH84 digital-to-analog converter (DAC) with 32-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO and (...)

Features
  • Comprehensive test capability for the DAC34SH84
  • Direct connection to TSW1400/TSW3100 signal generator
  • Includes CDCE62005 for clock generation or jitter cleaning
  • Software support with a full featured GUI for easy testing and prototyping
  • FMC-DAC-Adapter card compatible to connect with FMC interconnect (...)
  • EVALUATION BOARD Download
    299
    Description

    The LMK04800 family is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a (...)

    Features
    • Multi-mode: Dual PLL, single PLL, and clock distribution
    • Dual Loop PLLatinum PLL Architecture
        - PLL1
          > Holdover mode when input clocks are lost
            + Automatic or manual triggering/recovery
        - PLL2
          > Integrated Low-Noise VCO
    • 2 redundant input clocks with LOS
        - Automatic and manual switch-over modes
    • 50% duty cycle (...)
    EVALUATION BOARD Download
    499
    Description

    The TSW1265EVM is a wideband dual receiver reference design and evaluation platform. The signal chain allows conversion from RF to bits using a dual-channel downconverter mixer, the LMH6521 dual-channel DVGA, and the ADS4249 14-bit 250-MSPS ADC. The TSW1265EVM also includes the LMK04800 dual-PLL (...)

    Features
  • Complete RF-to-bits receiver evaluation platform utilizing a dual-channel downconverter, LMH6521 DVGA, and ADS4249 14-bit 250-MSPS ADC
  • The LMK04800 clock generator and jitter-cleaning provides a complete onboard clocking solution
  • A software GUI is provided to configure the ADS4249, LMK04800, and (...)
  • EVALUATION BOARD Download
    499
    Description

    The TSW3084EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW3084EVM includes (...)

    Features
  • Includes LMK04806B for clock generation and jitter cleaning
  • Direct connection to TSW3100/TSW1400/TSW1406 signal generator
  • Comprehensive test capability for the transmitter (DAC3484 quad DAC and two TRF3705 IQ Modulators) at analog baseband, IF and RF outputs
  • Software support with a full featured GUI (...)
  • EVALUATION BOARD Download
    499
    Description

    The TSW30H84EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (Please see LMK04800) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the (...)

    Features
  • Includes LMK04806B (Please see LMK04800) for clock generation and jitter cleaning
  • Direct connection to TSW1400/TSW1406/TSW3100 TSW1406 signal generator
  • Comprehensive test capability for the transmitter (DAC34H84 quad DAC and two TRF3705 IQ Modulators) at RF outputs
  • Software support with a full featured (...)
  • EVALUATION BOARD Download
    499
    Description

    The TSW30SH84EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04800 low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW30SH84EVM includes (...)

    Features
  • Includes LMK04800 for clock generation and jitter cleaning
  • Direct connection to TSW1400/TSW1406/TSW3100 pattern generator
  • Comprehensive test capability for the transmitter; DAC34SH84 quad DAC and two TRF3705 IQ Modulators with RF outputs
  • Software support with a full featured GUI for easy testing and (...)
  • Software development

    APPLICATION SOFTWARE & FRAMEWORK Download
    Clock Design Tool - Loop Filter & Device Configuration + Simulation
    CLOCKDESIGNTOOL The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)
    GUI FOR EVALUATION MODULE (EVM) Download
    SLAC507B.ZIP (123888 KB)
    GUI FOR EVALUATION MODULE (EVM) Download
    SLAC532.ZIP (126690 KB)
    IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
    CodeLoader Software for device register programming
    CODELOADER The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.


    Which software do I use?

    Product

    Loop (...)

    Design tools & simulation

    SIMULATION MODEL Download
    SNAM100C.ZIP (111 KB) - IBIS Model
    SIMULATION TOOL Download
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)

    CAD/CAE symbols

    Package Pins Download
    WQFN (NKD) 64 View options

    Ordering & quality

    Information included:
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    • Lead finish/Ball material
    • MSL rating/Peak reflow
    • MTBF/FIT estimates
    • Material content
    • Qualification summary
    • Ongoing reliability monitoring

    Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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