The LMK0480x family is the industry’s highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and varactor diode.
The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides low-noise jitter cleaner functionality while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet (Rev. K) | PDF | HTML | 24 Dec 2014 |
| User guide | TSW308x Evaluation Module (Rev. B) | 18 May 2016 | ||
| EVM User's guide | TSW4806EVM User's Guide (Rev. A) | 26 Apr 2016 | ||
| EVM User's guide | LMK0480x Evaluation Board Instructions (Rev. B) | 04 Aug 2014 | ||
| Technical article | Increasing dynamic performance in radar systems | 10 May 2014 | ||
| Design guide | TSW1265 Dual-Wideband RF-to-Digital Receiver Design Guide | 03 Sep 2013 | ||
| Application note | Using the LMK0480x/LMK04906 for Hitless Switching and Holdover | 12 Jul 2013 | ||
| Application note | Effects of Clock Noise on High Speed DAC Performance | 08 Nov 2012 | ||
| User guide | TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) | 29 Dec 2011 | ||
| Design guide | Clock Conditioner Owner's Manual | 10 Nov 2006 |
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| Package | Pins | Download |
|---|---|---|
| WQFN (NKD) | 64 | View options |
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