SBAS650C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.1 Using the Timer Module

The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles. These timing instants and the corresponding registers are listed in Table 8-2.

Note that the device does not restrict the values in these registers; thus, the start and end edges can be positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration of one clock cycle. The following steps describe the timer sequencing configuration:

  1. With respect to the start of the PRP period (indicated by timing instant t0 in Figure 8-13), the following sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1 ambient.
  2. Also, starting from t0, the sequence of sampling instants must be staggered with respect to the respective conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2.
  3. Finally, align the edges for the two LED pulses with the respective sampling instants.

Table 8-2 Clock Edge Mapping to SPI Registers
TIME INSTANT (See Figure 8-13 and Figure 8-14)(3)DESCRIPTIONCORRESPONDING REGISTER ADDRESS AND REGISTER BITSEXAMPLE(1) (Decimal)
t0Start of pulse repetition periodNo register control—
t1Start of sample LED2 pulseLED2STC[15:0], register 01h6050
t2End of sample LED2 pulseLED2ENDC[15:0], register 02h7998
t3Start of LED2 pulseLED2LEDSTC[15:0], register 03h6000
t4End of LED2 pulseLED2LEDENDC[15:0], register 04h7999
t5Start of sample LED2 ambient pulseALED2STC[15:0], register 05h50
t6End of sample LED2 ambient pulseALED2ENDC[15:0], register 06h1998
t7Start of sample LED1 pulseLED1STC[15:0], register 07h2050
t8End of sample LED1 pulseLED1ENDC[15:0], register 08h3998
t9Start of LED1 pulseLED1LEDSTC[15:0], register 09h2000
t10End of LED1 pulseLED1LEDENDC[15:0], register 0Ah3999
t11Start of sample LED1 ambient pulseALED1STC[15:0], register 0Bh4050
t12End of sample LED1 ambient pulseALED1ENDC[15:0], register 0Ch5998
t13Start of convert LED2 pulseLED2CONVST[15:0], register 0Dh
Must start one AFE clock cycle after the ADC reset pulse ends.		4
t14End of convert LED2 pulseLED2CONVEND[15:0], register 0Eh1999
t15Start of convert LED2 ambient pulseALED2CONVST[15:0], register 0Fh
Must start one AFE clock cycle after the ADC reset pulse ends.		2004
t16End of convert LED2 ambient pulseALED2CONVEND[15:0], register 10h3999
t17Start of convert LED1 pulseLED1CONVST[15:0], register 11h
Must start one AFE clock cycle after the ADC reset pulse ends.		4004
t18End of convert LED1 pulseLED1CONVEND[15:0], register 12h5999
t19Start of convert LED1 ambient pulseALED1CONVST[15:0], register 13h
Must start one AFE clock cycle after the ADC reset pulse ends.		6004
t20End of convert LED1 ambient pulseALED1CONVEND[15:0], register 14h7999
t21Start of first ADC conversion reset pulseADCRSTSTCT0[15:0], register 15h0
t22End of first ADC conversion reset pulse(2)ADCRSTENDCT0[15:0], register 16h3
t23Start of second ADC conversion reset pulseADCRSTSTCT1[15:0], register 17h2000
t24End of second ADC conversion reset pulse(2)ADCRSTENDCT1[15:0], register 18h2003
t25Start of third ADC conversion reset pulseADCRSTSTCT2[15:0], register 19h4000
t26End of third ADC conversion reset pulse(2)ADCRSTENDCT2[15:0], register 1Ah4003
t27Start of fourth ADC conversion reset pulseADCRSTSTCT3[15:0], register 1Bh6000
t28End of fourth ADC conversion reset pulse(2)ADCRSTENDCT3[15:0], register 1Ch6003
t29End of pulse repetition periodPRPCOUNT[15:0], register 1Dh7999
(1) Values are based off of a pulse repetition frequency (PRF) = 500 Hz and duty cycle = 25%.
(2) See Figure 8-14, note 2 for the effect of the ADC reset time crosstalk.
(3) Any pulse can be set to zero width by making its start value higher than the end value.
GUID-63CE9CAB-B3E5-4F55-BFF9-43A2D9AD41DC-low.gif
RED = LED2, IR = LED1.
A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28.
Figure 8-13 Programmable Clock Edges(1)(2)
GUID-C8A13F1F-2507-4E7A-B5E8-980AE86CB6B5-low.gif
RED = LED2, IR = LED1.
A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28.
Figure 8-14 Relationship Between the ADC Reset and ADC Conversion Signals(1)(2)