SLUSD20B july   2018  – april 2023 BQ25710

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up from Battery Without DC Source
      2. 9.3.2  Vmin Active Protection (VAP) when Battery only Mode
      3. 9.3.3  Power-Up From DC Source
        1. 9.3.3.1 CHRG_OK Indicator
        2. 9.3.3.2 Input Voltage and Current Limit Setup
        3. 9.3.3.3 Battery Cell Configuration
        4. 9.3.3.4 Device Hi-Z State
      4. 9.3.4  USB On-The-Go (OTG)
      5. 9.3.5  Converter Operation
        1. 9.3.5.1 Inductance Detection Through IADPT Pin
        2. 9.3.5.2 Continuous Conduction Mode (CCM)
        3. 9.3.5.3 Pulse Frequency Modulation (PFM)
      6. 9.3.6  Current and Power Monitor
        1. 9.3.6.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.6.2 High-Accuracy Power Sense Amplifier (PSYS)
      7. 9.3.7  Input Source Dynamic Power Manage
      8. 9.3.8  Two-Level Adapter Current Limit (Peak Power Mode)
      9. 9.3.9  Processor Hot Indication
        1. 9.3.9.1 PROCHOT During Low Power Mode
        2. 9.3.9.2 PROCHOT Status
      10. 9.3.10 Device Protection
        1. 9.3.10.1 Watchdog Timer
        2. 9.3.10.2 Input Overvoltage Protection (ACOV)
        3. 9.3.10.3 Input Overcurrent Protection (ACOC)
        4. 9.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.10.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.10.6 Battery Short
        7. 9.3.10.7 System Short Hiccup Mode
        8. 9.3.10.8 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  Setting Charge and PROCHOT Options
        1. 9.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
        2. 9.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 0211h]
        3. 9.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 02B7h]
        4. 9.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0030h]
        5. 9.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 4A65h]
        6. 9.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 81A0h]
        7. 9.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 9.6.2  Charge and PROCHOT Status
        1. 9.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 9.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = A800h]
      3. 9.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.3.1 Battery Precharge Current Clamp
      4. 9.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 9.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 9.6.5.1 System Voltage Regulation
      6. 9.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 9.6.6.1 Input Current Registers
          1. 9.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]
          2. 9.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 4100h]
          3. 9.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 9.6.7  OTGVoltage Register (SMBus address = 3Bh) [reset = 0000h]
      8. 9.6.8  OTGCurrent Register (SMBus address = 3Ch) [reset = 0000h]
      9. 9.6.9  ADCVBUS/PSYS Register (SMBus address = 23h)
      10. 9.6.10 ADCIBAT Register (SMBus address = 24h)
      11. 9.6.11 ADCIINCMPIN Register (SMBus address = 25h)
      12. 9.6.12 ADCVSYSVBAT Register (SMBus address = 26h)
      13. 9.6.13 ID Registers
        1. 9.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.8 OTGCurrent Register (SMBus address = 3Ch) [reset = 0000h]

To set the OTG output current limit, write to REG0x3C() using the data format listed in Figure 9-22, Table 9-39, and Table 9-40.

Figure 9-22 OTGCurrent Register (SMBus address = 3Ch) [reset = 0000h]
15141312111098
ReservedOTG Current set by host, bit 6OTG Current set by host, bit 5OTG Current set by host, bit 4OTG Current set by host, bit 3OTG Current set by host, bit 2OTG Current set by host, bit 1OTG Current set by host, bit 0
R/WR/WR/WR/WR/WR/WR/WR/W
76543210
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-39 OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
15ReservedR/W0b

Not used. 1 = invalid write.

14OTG Current set by host, bit 6R/W0b

0 = Adds 0 mA of OTG current.

1 = Adds 3200 mA of OTG current.

13OTG Current set by host, bit 5R/W0b

0 = Adds 0 mA of OTG current.

1 = Adds 1600mA of OTG current.

12OTG Current set by host, bit 4R/W0b

0 = Adds 0 mA of OTG current.

1 = Adds 800 mA of OTG current.

11OTG Current set by host, bit 3R/W0b

0 = Adds 0 mA of OTG current.

1 = Adds 400 mA of OTG current.

10OTG Current set by host, bit 2R/W0b

0 = Adds 0 mA of OTG current.

1 = Adds 200 mA of OTG current.

9OTG Current set by host, bit 1R/W0b

0 = Adds 0 mA of OTG current.

1 = Adds 100 mA of OTG current.

8OTG Current set by host, bit 0R/W0b

0 = Adds 0 mA of OTG current.

1 = Adds 50 mA of OTG current.

Table 9-40 OTGCurrent Register (SMBus address = 3Ch) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
7-0ReservedR/W00000000b

Not used. Value Ignored.