SLUSD20B july   2018  – april 2023 BQ25710

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up from Battery Without DC Source
      2. 9.3.2  Vmin Active Protection (VAP) when Battery only Mode
      3. 9.3.3  Power-Up From DC Source
        1. 9.3.3.1 CHRG_OK Indicator
        2. 9.3.3.2 Input Voltage and Current Limit Setup
        3. 9.3.3.3 Battery Cell Configuration
        4. 9.3.3.4 Device Hi-Z State
      4. 9.3.4  USB On-The-Go (OTG)
      5. 9.3.5  Converter Operation
        1. 9.3.5.1 Inductance Detection Through IADPT Pin
        2. 9.3.5.2 Continuous Conduction Mode (CCM)
        3. 9.3.5.3 Pulse Frequency Modulation (PFM)
      6. 9.3.6  Current and Power Monitor
        1. 9.3.6.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.6.2 High-Accuracy Power Sense Amplifier (PSYS)
      7. 9.3.7  Input Source Dynamic Power Manage
      8. 9.3.8  Two-Level Adapter Current Limit (Peak Power Mode)
      9. 9.3.9  Processor Hot Indication
        1. 9.3.9.1 PROCHOT During Low Power Mode
        2. 9.3.9.2 PROCHOT Status
      10. 9.3.10 Device Protection
        1. 9.3.10.1 Watchdog Timer
        2. 9.3.10.2 Input Overvoltage Protection (ACOV)
        3. 9.3.10.3 Input Overcurrent Protection (ACOC)
        4. 9.3.10.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.10.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.10.6 Battery Short
        7. 9.3.10.7 System Short Hiccup Mode
        8. 9.3.10.8 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)
    5. 9.5 Programming
      1. 9.5.1 SMBus Interface
        1. 9.5.1.1 SMBus Write-Word and Read-Word Protocols
        2. 9.5.1.2 Timing Diagrams
    6. 9.6 Register Map
      1. 9.6.1  Setting Charge and PROCHOT Options
        1. 9.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
        2. 9.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 0211h]
        3. 9.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 02B7h]
        4. 9.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0030h]
        5. 9.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 4A65h]
        6. 9.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 81A0h]
        7. 9.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h]
      2. 9.6.2  Charge and PROCHOT Status
        1. 9.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h]
        2. 9.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = A800h]
      3. 9.6.3  ChargeCurrent Register (SMBus address = 14h) [reset = 0000h]
        1. 9.6.3.1 Battery Precharge Current Clamp
      4. 9.6.4  MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting]
      5. 9.6.5  MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting]
        1. 9.6.5.1 System Voltage Regulation
      6. 9.6.6  Input Current and Input Voltage Registers for Dynamic Power Management
        1. 9.6.6.1 Input Current Registers
          1. 9.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h]
          2. 9.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 4100h]
          3. 9.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V]
      7. 9.6.7  OTGVoltage Register (SMBus address = 3Bh) [reset = 0000h]
      8. 9.6.8  OTGCurrent Register (SMBus address = 3Ch) [reset = 0000h]
      9. 9.6.9  ADCVBUS/PSYS Register (SMBus address = 23h)
      10. 9.6.10 ADCIBAT Register (SMBus address = 24h)
      11. 9.6.11 ADCIINCMPIN Register (SMBus address = 25h)
      12. 9.6.12 ADCVSYSVBAT Register (SMBus address = 26h)
      13. 9.6.13 ID Registers
        1. 9.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h]
        2. 9.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]

Figure 9-6 ChargeOption0 Register (SMBus address = 12h) [reset = E70Eh]
15141312111098
EN_LWPWRWDTMR_ADJIDPM_AUTO_
DISABLE		OTG_ON_
CHRGOK		EN_OOAPWM_FREQPTM_LL_EFF
R/WR/WR/WR/WR/WR/WR/W
76543210
ReservedSYS_SHORT
DISABLE		EN_LEARNIADPT_GAINIBAT_GAINEN_LDOEN_IDPMCHRG_INHIBIT
R/WR/WR/WR/WR/WR/WR/WR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-7 ChargeOption0 Register (SMBus address = 12h) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
15EN_LWPWRR/W1b

Low Power Mode Enable

0b: Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, current/power monitor buffer and comparator follow register setting.

1b: Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. The LDO is off. The PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. ADC is not available in Low Power Mode. Independent comparator can be enabled by setting either REG0X30()[14] or [13] to 1. <default at POR>

14-13WDTMR_ADJR/W11b

WATCHDOG Timer Adjust

Set maximum delay between consecutive SMBus write of charge voltage or charge current command.

If device does not receive a write on the REG0x15() or the REG0x14() within the watchdog time period, the charger will be suspended by setting the REG0x14() to 0 mA.

After expiration, the timer will resume upon the write of REG0x14(), REG0x15() or REG0x12[14:13]. The charger will resume if the values are valid.

00b: Disable Watchdog Timer

01b: Enabled, 5 sec

10b: Enabled, 88 sec

11b: Enable Watchdog Timer, 175 sec <default at POR>

12IDPM_AUTO_
DISABLE		R/W0b

IDPM Auto Disable

When CELL_BATPRESZ pin is LOW, the charger automatically disables the IDPM function by setting EN_IDPM (REG0x12[1]) to 0. The host can enable IDPM function later by writing EN_IDPM bit (REG0x12[1]) to 1.

0b: Disable this function. IDPM is not disabled when CELL_BATPRESZ goes LOW. <default at POR>

1b: Enable this function. IDPM is disabled when CELL_BATPRESZ goes LOW.

11OTG_ON_
CHRGOK		R/W0b

Add OTG to CHRG_OK

Drive CHRG_OK to HIGH when the device is in OTG mode.

0b: Disable <default at POR>

1b: Enable

10EN_OOAR/W1b

Out-of-Audio Enable

0b: No limit of PFM burst frequency

1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise <default at POR>

9PWM_FREQR/W1b

Switching Frequency

Two converter switching frequencies. One for small inductor and the other for big inductor.

Recommend 800 kHz with 2.2 µH or 3.3 µH, and 1.2 MHz with 1 µH or 1.5 µH.

0b: 1200 kHz

1b: 800 kHz <default at POR>

8LOW_PTM_
RIPPLE		R/W1b

PTM mode input voltage and current ripple reduction.

0b: Disable

1b: Enable <default at POR>

Table 9-8 ChargeOption0 Register (SMBus address = 12h) Field Descriptions
SMBus
BIT		FIELDTYPERESETDESCRIPTION
7ReservedR/W0bReserved
6SYS_SHORT_DISABLER/W0b

To disable the hiccup mode during the system short protection.

0b: When VSYS is short to lower than 2.4V, the charger enters hiccup mode <default at POR>

1b: The charger hiccup mode is disabled during system short fault

5EN_LEARNR/W0b

LEARN function allows the battery to discharge while the adapter is present. It calibrates the battery gas gauge over a complete discharge/charge cycle. When the battery voltage is below battery depletion threshold, the system switches back to adapter input by the host. When CELL_BATPRESZ pin is LOW, the device exits LEARN mode and this bit is set back to 0.

0b: Disable LEARN Mode <default at POR>

1b: Enable LEARN Mode

4IADPT_GAINR/W0b

IADPT Amplifier Ratio

The ratio of voltage on IADPT and voltage across ACP and ACN.

0b: 20× <default at POR>

1b: 40×

3IBAT_GAINR/W1b

IBAT Amplifier Ratio

The ratio of voltage on IBAT and voltage across SRP and SRN

0b: 8×

1b: 16× <default at POR>

2EN_LDOR/W1b

LDO Mode Enable

When battery voltage is below minimum system voltage (REG0x3E()), the charger is in precharge with LDO mode enabled.

0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery pack internal resistor. The system is regulated by the MaxChargeVoltage register.

1b: Enable LDO mode, Precharge current is set by the ChargeCurrent register and clamped below 384 mA (2 cell – 4 cell) or 2A (1 cell). The system is regulated by the MinSystemVoltage register. <default at POR>

1EN_IDPMR/W1b

IDPM Enable

Host writes this bit to enable IDPM regulation loop. When the IDPM is disabled by the charger (refer to IDPM_AUTO_DISABLE), this bit goes LOW.

0b: IDPM disabled

1b: IDPM enabled <default at POR>

0CHRG_INHIBITR/W0b

Charge Inhibit

When this bit is 0, battery charging will start with valid values in the MaxChargeVoltage register and the ChargeCurrent register.

0b: Enable Charge <default at POR>

1b: Inhibit Charge