The I²C serial communications interface in the BQ77307 device acts as a target device and supports rates up to 400 kHz with an optional CRC check. The BQ77307 will initially power up by default in a mode determined by the OTP settings factory programmed by TI. The host can change the CRC mode setting while in CONFIG_UPDATE mode, then the new setting will take effect upon exit of CONFIG_UPDATE mode.

The I²C device address (as an 8-bit value including target address and R/W bit) is set by default as 0x10 (write), 0x11 (read), which can also be changed by the configuration setting.

The communications interface includes programmable timeout capability, with the internal I²C bus logic reset when an enabled timeout occurs. This is described in detail in the BQ77307 Technical Reference Manual.

An I²C write transaction is shown in Figure 7-2. Block writes are allowed by sending additional data bytes before the Stop. The I²C logic will auto-increment the register address after each data byte. The shaded regions show when the device may be clock stretching.

Figure 7-2 I²C Write

The CRC check is enabled by setting a data memory bit. When enabled, the CRC is calculated as follows:

• Note that the CRC is reset after each data byte and after each stop.
• In a single-byte write transaction, the CRC is calculated over the target address, register address, and data.
• In a block write transaction, the CRC for the first data byte is calculated over the target address, register address, and data. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x⁸ + x² + x + 1, and the initial value is 0.

When the target detects an invalid CRC, the I²C target will NACK the CRC, which causes the I²C target to go to an idle state.

Figure 7-3 shows a read transaction using a Repeated Start. The shaded regions show when the device may be clock stretching.

Figure 7-3 I²C Read with Repeated Start

Figure 7-4 shows a read transaction where a Repeated Start is not used, for example if not available in hardware. For a block read, the controller ACK’s each data byte except the last and continues to clock the interface. The I²C block will auto-increment the register address after each data byte. The shaded regions show when the device may be clock stretching.

Figure 7-4 I²C Read Without Repeated Start

When enabled, the CRC for a read transaction is calculated as follows:

• Note that the CRC is reset after each data byte and after each stop.
• In a single-byte read transaction using a repeated start, the CRC is calculated beginning at the first start, so will include the target address, the register address, then the target address with read bit set, then the data byte.
• In a single-byte read transaction using a stop after the initial register address, the CRC is reset after the stop, so will only include the target address with read bit set and the data byte.
• In a block read transaction using repeated starts, the CRC for the first data byte is calculated beginning at the first start and will include the target address, the register address, then the target address with read bit set, then the data byte. The CRC for subsequent data bytes is calculated over the data byte only.
• In a block read transaction using a stop after the initial register address, the CRC is reset after the stop, so will only include the target address with read bit set and the first data byte. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x⁸ + x² + x + 1, and the initial value is 0.

When the controller detects an invalid CRC, the I²C controller will NACK the CRC, which causes the I²C target to go to an idle state.

For more information, see the BQ77307 Technical Reference Manual.