SNVS671F February   2011  – May 2019 LM21212-1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Circuit
  4. 4 Revision History
  5. 5 Description
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Performance Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Frequency Synchronization
      2. 8.3.2 Precision Enable
      3. 8.3.3 UVLO
      4. 8.3.4 Current Limit
      5. 8.3.5 Short-Circuit Protection
      6. 8.3.6 Thermal Protection
      7. 8.3.7 Power-Good Flag
      8. 8.3.8 Light Load Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Design Procedure
        1. 9.2.1.1 Custom Design With WEBENCH® Tools
        2. 9.2.1.2 Output Voltage
        3. 9.2.1.3 Precision Enable
        4. 9.2.1.4 Soft Start
        5. 9.2.1.5 Inductor Selection
        6. 9.2.1.6 Output Capacitor Selection
        7. 9.2.1.7 Input Capacitor Selection
        8. 9.2.1.8 Control Loop Compensation
      2. 9.2.2 Application Curves
  10. 10Layout
    1. 10.1 Pcb Layout Considerations
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With Webench® Tools
    2. 11.2 Receiving Notification Of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, And Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5 V. Minimum and maximum limits are specified through test, design, or statistical correlation, and, unless otherwise specified, apply over the junction temperature (TJ) range of −40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback pin voltage VIN = 2.95 V to 5.5 V –1% 0.6 1% V
ΔVOUT/ΔIOUT Load Regulation 0.02 %VOUT/A
ΔVOUT/ΔVIN Line Regulation 0.1 %VOUT/V
RDSON HS High Side Switch On Resistance ISW = 12 A 7 9 mΩ
RDSON LS Low Side Switch On Resistance ISW = 12A 4.3 6 mΩ
ICLR HS Rising Switch Current Limit 15 17 19 A
ICLF LS Falling Switch Current Limit 12 A
VZX Zero Cross Voltage TJ = 25°C –8 3 12 mV
IQ Operating Quiescent Current 1.5 3 mA
ISD Shutdown Quiescent Current VEN = 0V 50 70 µA
VUVLO AVIN Under Voltage Lockout AVIN Rising 2.45 2.70 2.95 V
VUVLOHYS AVIN Under Voltage Lockout Hysteresis 140 200 280 mV
VTRACKOS SS/TRACK PIN accuracy (VSS - VFB) 0 < VTRACK < 0.55 V – 10 6 20 mV
ISS Soft-Start Pin Source Current 1.3 1.9 2.5 µA
tINTSS Internal Soft-Start Ramp to Vref CSS = 0 350 500 675 µs
tRESETSS Device Reset to Soft-Start Ramp 50 110 200 µs
OSCILLATOR
fSYNCR SYNC Frequency Range 300 1500 kHz
fDEFAULT Default (no SYNC signal) Frequency 950 1000 1050 kHz
tSY_SW Time from SYNC falling to VSW Rising 200 ns
tSY_MIN Minimum SYNC pin pulse width, high or low 100 ns
tHSBLANK HS OCP Blanking Time Rising edge of SW to ICLR comparison 55 ns
tLSBLANK LS OCP Blanking Time Falling edge of SW to ICLF comparison 400 ns
tZXBLANK Zero Cross Blanking Time Falling edge of SW to VZX comparison 120 ns
tMINON Minimum HS on-time 140 ns
ΔVramp PWM Ramp p-p Voltage 0.8 V
ERROR AMPLIFIER
VOL Error Amplifier Open Loop Voltage Gain ICOMP = –65 µA to 1 mA 95 dBV/V
GBW Error Amplifier Gain-Bandwidth Product 11 MHz
IFB Feedback Pin Bias Current VFB = 0.6 V 1 nA
ICOMPSRC COMP Output Source Current 1 mA
ICOMPSINK COMP Output Sink Current 65 µA
POWERGOOD
VOVP Overvoltage Protection Rising Threshold VFB Rising 105 112.5 120 %VFB
VOVPHYS Overvoltage Protection Hysteresis VFB Falling 2 %VFB
VUVP Undervoltage Protection Rising Threshold VFB Rising 82 90 97 %VFB
VUVPHYS Undervoltage Protection Hysteresis VFB Falling 2.5 %VFB
tPGDGL PGOOD Deglitch Low (OVP/UVP Condition Duration to PGOOD Falling) 15 µs
tPGDGH PGOOD Deglitch High (minimum low pulse) 12 µs
RPGOOD PGOOD Pull-down Resistance 10 20 40 Ω
IPGOODLEAK PGOOD Leakage Current VPGOOD = 5V 1 nA
LOGIC
VIHSYNC SYNC Pin Logic High TJ = 25°C 2 V
VILSYNC SYNC Pin Logic Low TJ = 25°C 0.8 V
VIHENR EN Pin Rising Threshold VEN Rising 1.2 1.35 1.45 V
VENHYS EN Pin Hysteresis 50 110 180 mV
IEN EN Pin Pullup Current VEN = 0 V 2 µA
THERMAL SHUTDOWN
TTHERMSD Thermal Shutdown 165 °C
TTHERMSDHYS Thermal Shutdown Hysteresis 10 °C