9.2.1.8 Control Loop Compensation

The LM21212-1 incorporates a high bandwidth amplifier between the FB and COMP pins to allow the user to design a compensation network that matches the application. This section will walk through the various steps in obtaining the open loop transfer function.

There are three main blocks of a voltage mode buck switcher that the power supply designer must consider when designing the control system; the power train, modulator, and the compensated error amplifier. A closed loop diagram is shown in Figure 31.

Figure 31. Loop Diagram

The power train consists of the output inductor (L) with DCR (DC resistance R_DCR), output capacitor (C₀) with ESR (effective series resistance R_ESR), and load resistance (R_o). The error amplifier (EA) constantly forces FB to 0.6V. The passive compensation components around the error amplifier help maintain system stability. The modulator creates the duty cycle by comparing the error amplifier signal with an internally generated ramp set at the switching frequency.

There are three transfer functions that must be taken into consideration when obtaining the total open loop transfer function; COMP to SW (Modulator) , SW to V_OUT (Power Train), and V_OUT to COMP (Error Amplifier). The COMP to SW transfer function is simply the gain of the PWM modulator.

Equation 9.

where ΔV_RAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8 V). The SW to COMP transfer function includes the output inductor, output capacitor, and output load resistance. The inductor and capacitor create two complex poles at a frequency described by:

Equation 10.

In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a frequency described by:

Equation 11.

A Bode plot showing the power train response can be seen below.

Figure 32. Power Train Bode Plot

The complex poles created by the output inductor and capacitor cause a 180° phase shift at the resonant frequency as seen in Figure 32. The phase is boosted back up to -90° due to the output capacitor ESR zero. The 180° phase shift must be compensated out and phase boosted through the error amplifier to stabilize the closed loop response. The compensation network shown around the error amplifier in Figure 31 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies will stabilize the closed loop response. The Compensated Error Amplifier transfer function is:

Equation 12.

The pole located at the origin gives high open loop gain at DC, translating into improved load regulation accuracy. This pole occurs at a very low frequency due to the limited gain of the error amplifier, however, it can be approximated at DC for the purposes of compensation. The other two poles and two zeros can be located accordingly to stabilize the voltage mode loop depending on the power stage complex poles and Q. Figure 33 is an illustration of what the Error Amplifier Compensation transfer function will look like.

Figure 33. Type 3 Compensation Network Bode Plot

As seen in Figure 33, the two zeros (f_LC/2, f_LC) in the comensation network give a phase boost. This will cancel out the effects of the phase loss from the output filter. The compensation network also adds two poles to the system. One pole should be located at the zero caused by the output capacitor ESR (f_ESR) and the other pole should be at half the switching frequency (f_SW/2) to roll off the high frequency response. The dependancy of the pole and zero locations on the compensation components is described below.

Equation 13.

An example of the step-by-step procedure to generate compensation component values using the typical application setup (see Figure 38) is given. The parameters needed for the compensation values are given in the table below.

where ΔV_RAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8V), and f_CROSSOVER is the frequency at which the open-loop gain is a magnitude of 1. It is recommended that the f_crossover not exceed one-fifth of the switching frequency. The output capacitance, C_O, depends on capacitor chemistry and bias voltage. For Multi-Layer Ceramic Capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased. Measuring the actual capacitance value for the output capacitors at the output voltage is recommended to accurately calculate the compensation network. The example given here is the total output capacitance using the three MLCC output capacitors biased at 1.2V, as seen in the typical application schematic, Figure 38. Note that it is more conservative, from a stability standpoint, to err on the side of a smaller output capacitance value in the compensation calculations rather than a larger, as this will result in a lower bandwidth but increased phase margin.

First, a the value of R_FB1 should be chosen. A typical value is 10kΩ. From this, the value of R_C1 can be calculated to set the mid-band gain so that the desired crossover frequency is achieved:

Equation 14.

Next, the value of C_C1 can be calculated by placing a zero at half of the LC double pole frequency (f_LC):

Equation 15.

Now the value of C_C2 can be calculated to place a pole at half of the switching frequency (f_SW):

Equation 16.

R_C2 can then be calculated to set the second zero at the LC double pole frequency:

Equation 17.

Last, C_C3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor ESR:

Equation 18.

An illustration of the total loop response can be seen in Figure 34.

Figure 34. Loop Response

It is important to verify the stability by either observing the load transient response or by using a network analyzer. A phase margin between 45° and 70° is usually desired for voltage mode systems. Excessive phase margin can cause slow system response to load transients and low phase margin may cause an oscillatory load transient response. If the load step response peak deviation is larger than desired, increasing f_CROSSOVER and recalculating the compensation components may help but usually at the expense of phase margin.