SCLS374P May   1997  – April 2024 SN74AHCT595

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Handling Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Noise Characteristics
    9. 5.9  Operating Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • DB|16
  • PW|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Requirements

over recommended operating free-air temperature range, VCC = 5V ± 0.5V (unless otherwise noted) (see Figure 6-1)
PARAMETER TA = 25°C SN54AHCT595(1) SN74AHCT595 UNIT
MIN MAX MIN MAX MIN MAX
tw Pulse duration SRCLK high or low 5 5.5 5.5 ns
RCLK high or low 5 5.5 5.5
SRCLR low 5 5 5
tsu Setup time SER before SRCLK↑ 3 3 3 ns
SRCLK↑ before RCLK↑(2) 5 5 5
SRCLR low before RCLK↑ 5 5 5
SRCLR high (inactive) before SRCLK↑ 3.4 3.8 3.8
th Hold time SER after SRCLK↑ 2 2 2 ns
(1) Product Preview
(2) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.
GUID-FC15D0D8-111F-40A6-AA11-7FF6562968C1-low.gifFigure 5-1 Timing Diagram