SLAS965D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255 for next read or write command.
Register No | Description | Register No | Description | |
---|---|---|---|---|
Page 0 | 44 | Clock missing detection period | ||
0 | Page Select register | 59 | Auto mute time | |
1 | Analog control register | 60-64 | Reserved | |
2 | Standby, Powerdown requests | 65-66 | Auto mute enable and delay | |
3 | Mute | 67-82 | Reserved | |
4 | PLL Lock Flag, PLL enable | 83-85 | GPIOn output selection | |
5 | Reserved | 86,87 | GPIO control | |
6 | Reserved | 88,89 | Reserved | |
7 | De-emphasis enable, SDOUT select | 90 | DSP overflow | |
8 | GPIO enables & Mute Control | 91-94 | Sample rate status | |
9 | BCLK, LRCLK configuration | 95-107 | Reserved | |
10 | DSP GPIO Input | 108 | Analog mute monitor | |
11 | Reserved | 109-118 | Reserved | |
12 | Master Mode BCLK, LRCLK reset | 119 | GPIO input | |
13 | PLL clock source select | 120 | Auto mute flags | |
14-19 | Reserved | 121-125 | Reserved | |
20-24 | PLL dividers | Page 1 | ||
25,26 | Reserved | 1 | Reserved | |
27 | DSP clock divider | 2 | Analog gain control | |
28 | DAC clock divider | 3,4 | Reserved | |
29 | NCP clock divider | 5 | Undervoltage protection | |
30 | OSR clock divider | 6 | Analog mute control | |
31 | Reserved | 7 | Analog gain boost | |
32,33 | Master mode dividers | 8 | REF BG Fast | |
34 | FS speed mode | 9-15 | Reserved | |
35,36 | IDAC number of DSP clock cycles available in one audio frame) | Page 44 | ||
37 | Ignore various errors | 1 | Coefficient memory (CRAM) control | |
38,39 | Reserved | Pages 44-52 | Coefficient buffer – A (256 coeffs x 24 bits) | |
40,41 | I2S configuration | Pages 62-70 | Coefficient buffer – B (256 coeffs x 24 bits) | |
42 | DAC data path | Pages 152-186 | Instruction buffer (1024 instruction x 24 bits), I512 – I1023 are reserved | |
43 | Reserved | Pages 187-255 | Reserved |