SLOS930B November   2015  – November 2019 THS4541-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Single to Differential Gain of 2, 2-VPP Output
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (Vs+) – Vs– = 5 V
    6. 7.6 Electrical Characteristics: (Vs+) – Vs– = 3 V
    7. 7.7 Typical Characteristics
      1. 7.7.1 5-V Single Supply
      2. 7.7.2 3-V Single Supply
      3. 7.7.3 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Frequency-Response Shape Factors
    3. 8.3 I/O Headroom Considerations
    4. 8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 8.5 Noise Analysis
    6. 8.6 Factors Influencing Harmonic Distortion
    7. 8.7 Driving Capacitive Loads
    8. 8.8 Thermal Analysis
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Terminology and Application Assumptions
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 TINA Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.3 3-V to 5-V Supply Range

at Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≈ 25°C (unless otherwise noted)
THS4541-Q1 D037_SLOS375.gif
Figure 37. Main Amplifier Differential Open-Loop Gain and Phase vs Frequency
THS4541-Q1 D039_SLOS375.gif
Figure 39. Input Spot Noise Over Frequency
THS4541-Q1 D041_SLOS375.gif
Common-mode in to differential out, gain of 2 simulation
Figure 41. CMRR Over Frequency
THS4541-Q1 D043_SLOS375.gifFigure 43. Common-Mode, Small- and Large-Signal Response (Vocm pin driven)
THS4541-Q1 D045_SLOS375.gif
Vocm input either driven to midsupply by low impedance source, or allowed to float and default to midsupply
Figure 45. Output Common-Mode Noise
THS4541-Q1 D047_SLOS375.gif
Single-ended to differential gain of 2 (see Figure 61), PSRR for negative supply to differential output (1-kHz simulation)
Figure 47. –PSRR vs Vocm Approaching Vs–
THS4541-Q1 D049_SLOS375.gif
3 lots, total of 2962 units trimmed at 5-V supply
Figure 49. Input Offset Voltage
THS4541-Q1 D051_SLOS375.gif
5-V and 3-V delta from 25°C VIO, 25 units
Figure 51. Input Offset Voltage Over Temperature
THS4541-Q1 D053_SLOS375.gif
–40°C to +125°C endpoint drift, 3 lots, total of 68 units
Figure 53. Input Offset Voltage Drift
THS4541-Q1 D055_SLOS375.gif
Maximum differential output swing, Vocm at midsupply
Figure 55. Maximum Vopp vs Rload
THS4541-Q1 D057_SLOS375.gif
Vocm input floating, 3 lots, total of 2962 units
Figure 57. Common-Mode Output Offset from Vs+ / 2
Default Value
THS4541-Q1 D059_SLOS375.gif
10 MHz, 1-Vpp input single to differential gain of 2, see Figure 63
Figure 59. PD Turn On Waveform
THS4541-Q1 D038_SLOS375.gif
Single-ended input to differential output, simulated differential output impedance, (closed-loop) gain of 2 and 5, see Figure 61
Figure 38. Closed-Loop Output Impedance
THS4541-Q1 D040_SLOS375.gif
Single-ended input to differential output, gain of 2 (see Figure 61), simulated with 1% resistor, worst-case mismatch
Figure 40. Output Balance Error Over Frequency
THS4541-Q1 D042_SLOS375.gif
Single-ended to differential, gain of 2 (see Figure 61) PSRR simulated to differential output
Figure 42. PSRR Over Frequency
THS4541-Q1 D044_SLOS375.gifFigure 44. Common-Mode, Small- and Large-Step Response (Vocm pin driven)
THS4541-Q1 D046_SLOS375.gif
Average Vocm output offset of 37 units,
Standard deviation < 2.5 mV, see Figure 63
Figure 46. Vocm Offset vs Vocm Setting
THS4541-Q1 D048_SLOS375.gif
Single-ended to differential gain of 2 (see Figure 61), PSRR for positive supply to differential output (1-kHz simulation)
Figure 48. +PSRR vs Vocm Approaching Vs+
THS4541-Q1 D050_SLOS375.gif
3 lots, total of 2962 units
Figure 50. Input Offset Current
THS4541-Q1 D052_SLOS375.gif
5-V and 3-V over temperature IOS, 25 units
Figure 52. Input Offset Current Over Temperature
THS4541-Q1 D054_SLOS375.gif
–40°C to +125°C endpoint drift, 3 lots, total of 68 units
Figure 54. Input Offset Current Drift
THS4541-Q1 D056_SLOS375.gif
Figure 56. Supply Current vs PD Voltage
THS4541-Q1 D058_SLOS375.gif
Input driven midsupply, 3 lots, total of 2962 units
Figure 58. Common-Mode Output Offset from Driven Vocm
THS4541-Q1 D060_SLOS375.gif
10 MHz, 1-VPP input single to differential gain of 2, see Figure 63
Figure 60. PD Turn Off Waveform