SLOS930B November   2015  – November 2019 THS4541-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Single to Differential Gain of 2, 2-VPP Output
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (Vs+) – Vs– = 5 V
    6. 7.6 Electrical Characteristics: (Vs+) – Vs– = 3 V
    7. 7.7 Typical Characteristics
      1. 7.7.1 5-V Single Supply
      2. 7.7.2 3-V Single Supply
      3. 7.7.3 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Frequency-Response Shape Factors
    3. 8.3 I/O Headroom Considerations
    4. 8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 8.5 Noise Analysis
    6. 8.6 Factors Influencing Harmonic Distortion
    7. 8.7 Driving Capacitive Loads
    8. 8.8 Thermal Analysis
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Terminology and Application Assumptions
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 TINA Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.1 5-V Single Supply

at Vs+ = 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA ≈ 25°C (unless otherwise noted)
THS4541-Q1 D001_SLOS375.gif
Rf = 402 Ω, see Figure 61 and Table 6 for resistor values
Figure 1. Small-Signal Frequency Response vs Gain
THS4541-Q1 D003_SLOS375.gif
Vout = 100 mVPP , see Figure 61 with Vocm adjusted
Figure 3. Small-Signal Frequency Response vs Vocm
THS4541-Q1 D005_SLOS375.gif
100 mVPP at load, Av = 2 (see Figure 71), two series Ro added at output before Cload
Figure 5. Small-Signal Frequency Response vs Cload
THS4541-Q1 D007_SLOS375.gif
50-MHz input, 0.3-ns input edge rate, single-ended to differential output, DC coupled, see Figure 63
Figure 7. Small- and Large-Signal Step Response
THS4541-Q1 D009_SLOS375.gif
G = 5 V/V, 50-MHz input, 0.3-ns input edge rate, single-ended input to differential output, see Figure 63
Figure 9. Small- and Large-Signal Step Response
THS4541-Q1 D011_SLOS375.gif
Simulated with 2-ns input transition time, see Figure 63
Figure 11. Small- and Large-Signal Step Settling Time
THS4541-Q1 D013_SLOS375.gif
2-VPP output, see Figure 61
Figure 13. Harmonic Distortion Over Frequency
THS4541-Q1 D015_SLOS375.gif
1 VPP each tone, see Figure 61
Figure 15. IMD2 and IM3 Over Frequency
THS4541-Q1 D017_SLOS375.gif
f = 10 MHz, 2-VPP output, see Figure 63 with Vocm adjusted
Figure 17. Harmonic Distortion vs Vocm
THS4541-Q1 D002_SLOS375.gif
See Figure 61
Figure 2. Frequency Response vs Vopp
THS4541-Q1 D004_SLOS375.gif
Vout = 100 mVPP, see Figure 61 with RL adjusted
Figure 4. Small-Signal Frequency Response vs Rload (RL)
THS4541-Q1 D006_SLOS375.gif
Ro is two series output resistors to a differential Cload in parallel with 500 Ω, see Figure 71 and Table 6
Figure 6. Recommended Ro vs Cload
THS4541-Q1 D008_SLOS375.gif
Av = 2 , 500-mVPP output into 22-pF Cload, see Figure 71
Figure 8. Step Response into Capacitive Load
THS4541-Q1 D010_SLOS375.gif
G = 5 V/V, 500-mVPP output into 22-pF Cload, see Figure 71 and Table 6
Figure 10. Step Response into Capacitive Load
THS4541-Q1 D012_SLOS375.gif
Single-ended to differential gain of 2 (see Figure 63), 2x input overdrive
Figure 12. Overdrive Recovery Performance
THS4541-Q1 D014_SLOS375.gif
10 MHz, see Figure 61
Figure 14. Harmonic Distortion vs Output Swing
THS4541-Q1 D016_SLOS375.gif
f = 10 MHz, see Figure 61 with Rload adjusted
Figure 16. Harmonic Distortion vs Rload
THS4541-Q1 D018_SLOS375.gif
10 MHz, 2-VPP output, see Figure 61 and Table 6 for gain setting
Figure 18. Harmonic Distortion vs Gain