8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances

The THS4541-Q1 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to +125°C operating range. This offset voltage combines with several other error contribution terms to produce an initial 25°C differential offset error band, and then a drift over temperature. For each error term, a gain must be assigned to that term. For this analysis, only DC-coupled signal paths are considered. One new source of output error (versus typical op amp analysis) arises from the effect that mismatched resistor values and ratios can have on the two sides of the FDA. Any common-mode voltage or drift creates a differential output error through the slight mismatches arising from the external feedback and gain-setting resistor tolerances, and the approximation (or snap) to standard value.

The error terms (25°C and drift), along with the gain to the output differential voltage, include:

• Input offset voltage—this voltage has a gain equal to the noise gain or 1 + Rf / Rg, where Rg is the total DC impedance from the input pins back to the source, or a DC reference (typically ground).
• Input offset current—this current has a gain to the differential output through the average feedback resistor value.

The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias current creating a differential output offset because of Rf mismatch. For simplicity, the upper Rf and Rg values are called Rf1 and Rg1 with a ratio of Rf1 / Rg1 ≡ G1. The lower elements are defined as Rf2 and Rg2 with a ratio of Rf2 / Rg2 ≡ G2. To compute worst-case contributions, a maximum variation in the design resistor tolerance is used in the absolute and ratio mismatches. For instance, ±1% tolerance resistors are assumed, giving a worst-case G1 that is 2% higher than nominal and a G2 that is 2% lower than nominal, with a worst-case Rf value mismatch of 2% as well. For matched impedance designs with Rt and Rg1 on a single-ended to differential stage, the standard value snap imposes a fixed mismatch in the initial feedback ratios with the resistor tolerance adding a mismatch to this initial ratio mismatch. Define the selected external resistor tolerance as ±T (so for 1% tolerance resistors, T = 0.01).

• Total gain for bias current error is ±2 × T × Rfnom

Anything that generates an output common-mode level or shift over temperature also generates an output differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in the output common-mode is overridden by the common-mode control loop, where any feedback ratio mismatch creates a balanced, differential error around the Vocm output.

The terms that create a differential error from a common-mode term and feedback ratio mismatch include the desired Vocm voltage, any source common-mode voltage, any drift on the reference bias to the Vocm control pin, and any internal offset and drift in the Vocm control path.

Considering just the output common-mode control and the source common-mode voltage (Vicm), the conversion to output differential offsets is done by using Equation 4:

Equation 4.

Neglecting any G1 and G2 mismatch because of standard values snap, the conversion gain for these two terms can be recast in terms of the nominal Rf / Rg ≡ G, and tolerance T, as shown in Equation 5. As G increases, this conversion gain approaches 4T, as a worst-case gain for these terms to output differential offset.

Equation 5.

This conversion gain to differential output error is applied to two error terms: Vocm, assuming the input control pin is driven and not floating, and the source Vicm voltage. The source common-mode voltage is assumed to be 0 V in this example. If not, apply this gain to the source common-mode value or range in the intended application.

As a full example of using these terms to estimate the worst-case output 25°C error band, and then the worst-case drift (by adding all the error terms together independently), use the gain of 2 V/V configuration of Figure 63 with Rf = 402 Ω, and assume ±1% tolerance on the resistors with the standard values used in Figure 69.

Figure 69. DC-Coupled Gain of 2 with Rf = 402 Ω and a Single-Ended to Differential Matched Input 50-Ω Impedance

The standard value snap on the signal-input side actually produces added G mismatch along with the resistor tolerances. For Figure 69, G2 = 402 / 221 = 1.819; and G1 = 402 / 218.3 = 1.837 nominally, with a ±2% tolerance around this initial mismatch for G2 and G1, if 1% resistors are used.

Using the maximum 25°C error terms, and a nominal 2.5-V input to the Vocm control pin, gives Table 3 with the error terms, the gains to the output differential error (Vod), and then the summed output error band at 25°C.

The 0.03222 conversion gain for the G ratio mismatch is the worst case, starting from the initially higher G1 value because of standard value snap, and using a ±1% tolerance on the Rf and Rg elements of that ratio. The actual Vocm conversion gain range is not symmetric, but is shown that way here. The initial 25°C worst-case error band is dominated by the Vocm conversion to Vod through the feedback resistor ratio mismatch. Improve this G match and tolerances to reduce this term.

Normally, the expected drift in the output Vod is of more interest than an initial error band. Table 4 shows these terms and the summed results, adding all the terms independently to obtain a worst-case drift.

In this calculation, the input offset voltage drift dominates the output differential offset drift. For the last term, the drift for the Vocm path is just for the internal offset drift of the common-mode path. Make sure to also consider the added external drift on the source of the Vocm input.

The absolute accuracy and drift for the THS4541-Q1 are exceptionally good. Mismatched resistor feedback ratios combined with a high drift in the Vocm control input can actually dominate the output Vod drift. Where the output differential precision is more important than the input matching accuracy, consider matching the networks on the two input sides to achieve improved nominal G1 to G2 match. The gains for the input bias current error terms are relatively low in this example design using 402-Ω feedback values. Higher Rf values give these terms more gain. A less conservative estimate of output drift considers the terms to be uncorrelated and RMS half of each terms worst-case span shown in Table 4. Performing this calculation for this example estimates a less conservative output offset drift of ±3.42 µV/°C; essentially, half the worst-case span of the input offset drift term. Follow these steps to estimate the output differential offset and drift for any external configuration.