SLOS930B November   2015  – November 2019 THS4541-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Single to Differential Gain of 2, 2-VPP Output
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (Vs+) – Vs– = 5 V
    6. 7.6 Electrical Characteristics: (Vs+) – Vs– = 3 V
    7. 7.7 Typical Characteristics
      1. 7.7.1 5-V Single Supply
      2. 7.7.2 3-V Single Supply
      3. 7.7.3 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Frequency-Response Shape Factors
    3. 8.3 I/O Headroom Considerations
    4. 8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 8.5 Noise Analysis
    6. 8.6 Factors Influencing Harmonic Distortion
    7. 8.7 Driving Capacitive Loads
    8. 8.8 Thermal Analysis
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Terminology and Application Assumptions
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 TINA Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics: (Vs+) – Vs– = 3 V

at TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs (unless otherwise noted); see Figure 61 for an AC-coupled gain of a 2-V/V test circuit, and Figure 63 for a DC-coupled gain of a 2-V/V test circuit
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST
LEVEL(1)
AC PERFORMANCE
Small-signal bandwidth Vout = 100 mVPP, G = 1 600 MHz C
Vout = 100 mVPP, G = 2 (see Figure 61) 500 C
Vout = 100 mVPP, G = 5 200 C
Vout = 100 mVPP, G = 10 120 C
Gain-bandwidth product Vout = 100 mVPP, G = 20 850 MHz C
Large-signal bandwidth Vout = 2 VPP, G = 2 (see Figure 61) 300 MHz C
Bandwidth for 0.1-dB flatness Vout = 2 VPP, G = 2 (see Figure 61) 90 MHz C
Slew rate(2) Vout = 2-V step, FPBW (see Figure 61) 1300 V/µs C
Rise/fall time Vout = 2-V step, G = 2, input ≤ 0.3 ns tr
(see Figure 63)		 1.8 ns C
Settling time To 1%, Vout = 2-V step, tr = 2 ns, G = 2
(see Figure 63)		 5 ns C
To 0.1%, Vout = 2-V step, tr = 2 ns, G = 2
(see Figure 63)		 8 C
Overshoot and undershoot Vout = 2-V step G = 2, input ≤ 0.3 ns tr
(see Figure 63)		 10% C
100-kHz harmonic distortion Vout = 2 VPP, G = 2, HD2 (see Figure 61) –140 dBc C
Vout = 2 VPP, G = 2, HD3 (see Figure 61) –140 C
10-MHz harmonic distortion Vout = 2 VPP, G = 2, HD2 (see Figure 61) –92 dBc C
Vout = 2 VPP, G = 2, HD3 (see Figure 61) –89 C
2nd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 61)		 –89 dBc C
3rd-order intermodulation distortion f = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 61)		 –87 dBc C
Input voltage noise f > 100 kHz 2.2 nV/√Hz C
Input current noise f > 1 MHz 1.9 pA/√Hz C
Overdrive recovery time 2X output overdrive, either polarity 20 ns C
Closed-loop output impedance f = 10 MHz (differential) 0.1 Ω C
DC PERFORMANCE
AOL Open-loop voltage gain 100 119 dB A
Input-referred offset voltage TA = 25°C –450 ±100 400 µV A
TA = 0°C to 70°C –600 ±100 600 B
TA = –40°C to +85°C –700 ±100 700 B
TA = –40°C to +125°C –850 ±100 850 B
Input offset voltage drift(3) TA = –40°C to +125°C –2.4 ±0.5 2.4 µV/°C B
Input bias current
(positive out of node)		 TA = 25°C 4.1 9 12 µA A
TA = 0°C to 70°C 4.1 9 12.5 B
TA = –40°C to +85°C 4.1 9 13 B
TA = –40°C to +125°C 4.1 9 13.5 B
Input bias current drift(3) TA = –40°C to +125°C –5 15 nA/°C B
Input offset current TA = 25°C –500 ±150 500 nA A
TA = 0°C to 70°C –550 ±150 550 B
TA = –40°C to +85°C –580 ±150 580 B
TA = –40°C to +125°C –620 ±150 620 B
Input offset current drift(3) TA = –40°C to +125°C –1.3 ±0.3 1.3 nA/°C B
INPUT
Common-mode input low < 3-dB degradation in CMRR from midsupply TA = 25°C (Vs–) – 0.2 (Vs–) – 0.1 V A
TA = –40°C to +125°C (Vs–) – 0.1 Vs– B
Common-mode input high < 3-dB degradation in CMRR from midsupply TA = 25°C (Vs+) – 1.3 (Vs+) –1.2 V A
TA = –40°C to +125°C (Vs+) – 1.3 B
Common-mode rejection ratio Input pins at ((Vs+) – Vs–) / 2 85 100 dB A
Input impedance differential mode Input pins at ((Vs+) – Vs–) / 2 110 || 0.85 kΩ || pF C
OUTPUT
Output voltage low TA = 25°C (Vs–) + 0.2 (Vs–) + 0.25 V A
TA = –40°C to +125°C (Vs–) + 0.2 (Vs–) + 0.25 B
Output voltage high TA = 25°C (Vs+) – 0.25 (Vs+) – 0.2 V A
TA = –40°C to +125°C (Vs+) – 0.25 (Vs+) – 0.2 B
Output current drive TA = 25°C ±55 ±60 mA A
TA = –40°C to +125°C ±55 B
POWER SUPPLY
Specified operating voltage 2.7 3 5.4 V B
Quiescent operating current TA = 25°C, Vs+ = 3 V 9.3 9.7 10.1 mA A
TA = –40°C to +125°C 9 9.7 10.6 B
±PSRR Power-supply rejection ratio Either supply pin to differential Vout 85 100 dB A
POWER DOWN
Enable voltage threshold (Vs–) + 1.7 V A
Disable voltage threshold (Vs–) + 0.7 V A
Disable pin bias current PD = Vs– → Vs+ 20 50 nA B
Power-down quiescent current PD = (Vs–) + 0.7 V 2 30 µA A
PD = Vs– 1.0 8.0 A
Turn-on time delay Time from PD = low to Vout = 90% of final value 100 ns C
Turn-off time delay Time from PD = low to Vout = 10% of final value 60 ns C
OUTPUT COMMON-MODE VOLTAGE CONTROL(4)
Small-signal bandwidth Vocm = 100 mVPP 140 MHz C
Slew rate(2) Vocm = 1-V step 350 V/µs C
Gain 0.975 0.987 0.990 V/V A
Input bias current Considered positive out of node –0.7 0.1 0.7 µA A
Input impedance Vocm input driven to ((Vs+) – Vs–) / 2 47 || 1.2 kΩ || pF C
Default voltage offset from
((Vs+) – Vs–) / 2		 Vocm pin open –40 ±10 40 mV A
CM Vos Common-mode offset voltage Vocm input driven to ((Vs+) – Vs–) / 2 TA = 25°C –5 ±2 5 mV A
TA = 0°C to 70°C –5.8 ±2 5.8 B
TA = –40°C to +85°C –6.2 ±2 6.2 B
TA = –40°C to +125°C –7 ±2 7 B
Common-mode offset voltage drift(3) Vocm input driven to ((Vs+) – Vs–) / 2 –20 ±4 20 µV/°C B
Common-mode loop supply headroom to negative supply < ±12-mV shift from midsupply CM Vos TA = 25°C 0.88 V A
TA = 0°C to 70°C 0.91 B
TA = –40°C to +85°C 0.94 B
TA = –40°C to +125°C 0.94 B
Common-mode loop supply headroom to positive supply < ±12-mV shift from midsupply CM Vos TA = 25°C 1.1 V A
TA = 0°C to 70°C 1.15 B
TA = –40°C to +85°C 1.2 B
TA = –40°C to +125°C 1.2 B
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π · f–3dB.
(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
(4) Specifications are from input Vocm pin to differential output average voltage.