SBOSA15A september 2022 – may 2023 TMP1827
PRODUCTION DATA
Figure 9-5 shows the 8-bit IO hardware address mode of the device. This feature is available on packages which have general-purpose pins (IO0-IO3) available. The 8-bit value consists of the lower 4 bits as read values of the pins (IO3 to IO0) that is overlaid on the contents of the short address register to form a 8-bit address. The application may connect the general-purpose pins to either VDD/SDQ for logic '1' or GND for logic '0'. TI recommends to use a 20 KΩ resistor to be placed between the IO and VDD/SDQ to prevent a supply shot in case the IO pin is accidentally set to zero in output mode.
After having FLEX_ADDR_MODE as '00b', the host must set the bits as '01b' in the device configuration-2 register for the device to latch the state of the general-purpose pins.