10 Revision
History
Changes from April 2, 2024 to September 19, 2024
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This Revision History lists the changes from SPRSP85 to
SPRSP85A.
Go
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Global: TI is transitioning to use more inclusive
terminology. Some language may be different than what you would expect to see
for certain technology areas. For SPI, all instances of legacy
terminology have been changed to controller and peripheral. All instances of
legacy pin names have been changed to: POCI (Peripheral OUT Controller IN); PICO
(Peripheral IN Controller OUT); and CS (Chip Select). For the I2C Bus
Interface, all instances of legacy terminology have been changed to
controller and target. For the CAN and LIN Interface/BUS, all instances
of legacy terminology have been changed to commander and responder. For the
EtherCAT Controller, all instances of legacy terminology have been
changed to MainDevice (or MDevice) and SubordinateDevice (or
SubDevice).Go
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Global: Changed document status statement from "ADVANCE
INFORMATION for preproduction products; subject to change without notice" to
"UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA".Go
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Global: Information on the TMS320F28P550SJ device is
Production Data.Go
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Global: Information on the TMS320F28P559SJ-Q1,
TMS320F28P559SG-Q1, and TMS320F28P550SG devices is preview information only (not
Production Data),Go
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Global: Removed TMS320F28P550SD device.Go
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Global: Changed "NNPU" to "NPU".Go
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Global: Changed DACB_OUT to CMP1_DACL.Go
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Features section: Removed "Neural-Network Processing Unit
(NNPU)" from "Real-time processing" features.Go
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Features section: Added Fast Serial Interface (FSI) to
Communications peripherals.Go
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Features section: Changed "24 ePWM channels with 16
channels that have high-resolution capability (150ps resolution)" to "24
ePWM channels with 12 channels that have high-resolution capability
(150ps resolution)".Go
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Features section: Added "Neural-network Processing Unit
(NPU)" features.Go
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Description section: Updated
applications link in "These include such
applications as". Added paragraph about
Neural-network Processing Unit (NPU).Go
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Package Information table: Added "Preview
information (not Production Data)"
footnote.Go
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Functional Block Diagram figure: Changed "24x ePWM Channels
(16Ch Hi-Res Capable)" to "24x ePWM Channels (12Ch Hi-Res
Capable)".Go
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Device Comparison table: Added "Preview information (not Production
Data)" footnote.Go
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Pin Attributes table: Changed DACB_OUT to
CMP1_DACL. Added footnotes about VREFLO and
VREFHI.Go
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128-pin PDT Thin Quad Flatpack (Top View) figure: Changed
DACB_OUT to CMP1_DACL on Pin 29.Go
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100-Pin PZ Low-Profile Quad Flatpack (Top View) figure:
Changed DACB_OUT to CMP1_DACL on Pin 22.Go
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80-Pin PNA Thin Quad Flatpack (Top View) figure: Changed
DACB_OUT to CMP1_DACL on Pin 18.Go
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64-Pin PM Low-Profile Quad Flatpack (Top View) figure:
Changed DACB_OUT to CMP1_DACL on Pin 14.Go
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56-Pin RSH Very Thin Quad Flatpack No-Lead (Top View) figure:
Changed DACB_OUT to CMP1_DACL on Pin 12.Go
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Analog Signals table: Removed DACB_OUT. Added footnotes about
VREFLO and VREFHI.Go
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Digital Inputs and Outputs on ADC Pins (AGPIOs) section:
Updated section.Go
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Absolute Maximum Ratings table: Removed reference to
"Continuous clamp current per pin is ±2mA" footnote from "Input clamp current -
total for all inputs".Go
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Electrical Characteristics table: Updated IOL,
ROL, and ILEAK. Added VIH (High-level input
voltage - GPIO23/41). Updated MIN values of
VHYSTERESIS.Go
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ESD Ratings – Commercial table: Added HBM value for 5V FS (fail-safe)
pins.Go
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ESD Ratings – Automotive table: Added HBM value for 5V FS (fail-safe)
pins.Go
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System Current Consumption -
VREG Enable - Internal Supply table: Updated
table.Go
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System Current Consumption -
VREG Disable - External Supply table: Updated
table.Go
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Typical Current Reduction per Disabled Peripheral table: Changed
"ePWM(per)" to "ePWM (for 1 ePWM)".Go
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Special Considerations for 5V Fail-Safe Pins section: Added
section.Go
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Clocking System figure: Updated figure.Go
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Internal Clock Frequencies
table: Added f(NPU), NPUCLK
frequency.Go
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Crystal Oscillator Specifications section: Removed duplicate
Crystal Oscillator Electrical Characteristics table.Go
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RAM Specifications section: Removed RAM Parameters –
F28P55xSD table.Go
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ROM Specifications section: Changed table title from ROM
Parameters – F28P55xSJ, F28P55xSG, and F28P55xSD to ROM Parameters –
F28P55xSJ and F28P55xSG.Go
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GPIO Electrical Data and Timing section:
Updated section.Go
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Analog Subsystem Block Diagram (128-/80-/64-/56-Pin Packages)
figure: Changed A1/B7/D11/DACB_OUT to
A1/B7/D11/CMP1_DACL.Go
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Analog Subsystem Block Diagram (100-Pin Package) figure:
Changed A1/B7/D11/DACB_OUT to
A1/B7/D11/CMP1_DACL.Go
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CMPSS Input Mux Options table: Changed "A1, B7, D11,
DACB_OUT" to "A1, B7, D11, CMP1_DACL" for HP4 and
LP4.Go
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Analog Pins and Internal Connections table: Changed
"A1/B7/D11/DACB_OUT" to "A1/B7/D11/CMP1_DACL" in Analog Group
1. Changed DACB_OUT to CMP1_DACL in Analog Group 1. Go
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Analog Signal Descriptions table: Changed DACB_OUT to
CMP1_DACL. Go
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ADC Characteristics table: Updated Offset Error, SNR, THD,
ENOB, and PSRR. Added "Frequency tolerance over temperature of the INTOSC ..."
footnote. Go
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ADC Performance Per Pin section: Added
section.Go
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Per-Channel Parasitic Capacitance for 128-Pin QFP table:
Updated table.Go
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Per-Channel Parasitic Capacitance for 100-Pin QFP table:
Updated table.Go
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Per-Channel Parasitic Capacitance for 80-Pin QFP table:
Updated table.Go
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Per-Channel Parasitic Capacitance for 64-Pin QFP table:
Updated table.Go
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Per-Channel Parasitic Capacitance for 56-Pin QFN table:
Updated table.Go
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Buffered Output from CMPx_DACL Electrical Characteristics
table: Updated MIN and MAX values of INL.Go
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PGA Characteristics table: Updated table and
footnotes.Go
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Overview section: Updated section.Go
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Functional Block Diagram figure: Changed "24x ePWM Channels
(16Ch Hi-Res Capable)" to "24x ePWM Channels (12Ch Hi-Res
Capable)".Go
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Flash Memory Map table: Updated table.Go
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Peripheral Registers Memory Map table: Updated
table.Go
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Device Identification Registers table: Removed PARTIDH for
TMS320F28P55xSD7. Added REVID for silicon revision A.Go
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Reference Design section: Updated section.Go
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Device Nomenclature figure: Updated figure.Go
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Package Symbolization for PDT Package – Automotive figure: Updated
definition of G4.Go
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Package Symbolization for PZ Package – Automotive figure: Updated
definition of G4.Go
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Package Symbolization for PZ Package – Non-Automotive figure: Updated
definition of G4. Updated device number.Go
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Package Symbolization for PNA Package – Automotive figure: Updated
definition of G4.Go
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Package Symbolization for PNA Package – Non-Automotive figure:
Updated definition of G4. Updated device number.Go
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Package Symbolization for PM Package – Automotive figure: Updated
definition of G4.Go
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Package Symbolization for PM Package – Non-Automotive figure: Updated
definition of G4. Updated device number.Go
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Package Symbolization for RSH Package – Non-Automotive figure:
Updated definition of G4. Updated device number.Go
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Revision Identification table: Changed REVID of Silicon Revision 0 to
0x0000 0001. Added silicon revision A.Go
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Documentation Support section: Added Migrating Software
From 8-Bit (Byte) Addressable CPUs to C28x CPU to Application Notes
section.Go
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Documentation Support section: Added Hardware Design Guide
for F2800x C2000™ Real-Time MCU Series Application
Note.Go