SPRSP85A April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
PRODMIX
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Digital and Analog IO | |||||||
VOH | High-level output voltage | IOH = IOH MIN | VDDIO * 0.8 | V | |||
IOH = –100 μA | VDDIO – 0.2 | ||||||
VOL | Low-level output voltage | IOL = IOL MAX | 0.4 | V | |||
IOL = 100 µA | 0.2 | ||||||
IOH | High-level output source current for all output pins | –4 | mA | ||||
IOL | Low-level output sink current for all output pins | 4 | mA | ||||
Low-level output sink current for GPIO2/3/9/32 | IO_DRVSEL:DRVSELGPIOx = 0 | 4 | mA | ||||
IO_DRVSEL:DRVSELGPIOx = 1 | 12 | mA | |||||
ROH | High-level output impedance for all output pins | VOH=VDDS-0.4V | 50 | 66 | 96 | Ω | |
ROL | Low-level output impedance for all output pins | VOL=0.4V | 48 | 60 | 84 | Ω | |
Low-level output impedance for GPIO2/3/9/32 | IO_DRVSEL:DRVSELGPIOx = 0 | 48 | 60 | 84 | Ω | ||
IO_DRVSEL:DRVSELGPIOx = 1 | 15 | 21 | 33 | Ω | |||
VIH | High-level input voltage | 2.0 | V | ||||
High-level input voltage - GPIO23/41 | 2.21 | V | |||||
High-level input voltage - GPIO2/3/9/32 | IO_MODSEL:MODSELGPIOx = 0 | 0.7*VDDIO | V | ||||
IO_MODSEL:MODSELGPIOx = 1 | 1.35 | V | |||||
VIL | Low-level input voltage | 0.8 | V | ||||
Low-level input voltage - GPIO2/3/9/32 | IO_MODSEL:MODSELGPIOx = 0 | 0.3*VDDIO | V | ||||
IO_MODSEL:MODSELGPIOx = 1 | 0.8 | V | |||||
VHYSTERESIS | Input hysteresis (AIO) | 115 | mV | ||||
Input hysteresis (GPIO) | 115 | ||||||
IPULLDOWN | Input current | Pins with pulldown | VDDIO = 3.3 V VIN = VDDIO |
120 | µA | ||
IPULLUP | Input current | Digital inputs with pullup enabled(1) | VDDIO = 3.3 V VIN = 0 V |
160 | µA | ||
RPULLDOWN | Weak pulldown resistance | 22 | 31 | 62 | kΩ | ||
RPULLUP | Weak pullup resistance | 19 | 29 | 54 | kΩ | ||
GPIO2/3/9/32 | 20 | 31 | 65 | kΩ | |||
ILEAK | Pin leakage | Digital inputs (all inputs except GPIO2/3/9/32) |
Pullups and outputs
disabled 0 V ≤ VIN ≤ VDDIO |
0.150 | µA | ||
Pin leakage (Device-powered). See the Special Considerations for 5V Fail-Safe Pins section. |
Digital inputs (GPIO2/3/9/32) | Pullups and outputs
disabled 0 V ≤ VIN ≤ 5.5 V VDDIO = 3.3 V |
30 | ||||
Pin leakage (Device-unpowered) |
Digital inputs (GPIO2/3/9/32) | Pullups and outputs
disabled 0 V ≤ VIN ≤ 5.5 V VDDIO = 0 V |
5 | ||||
Pin leakage | Analog pins | Analog drivers disabled 0 V ≤ VIN ≤ VDDA |
0.150 | ||||
CI | Input capacitance | Digital inputs | 2 | pF | |||
Analog pins(2) | |||||||
VREG and BOR | |||||||
VREG, POR, BOR(3) |