JAJSFC6C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PAT_PRBS_
LVDS5 |
PAT_PRBS_
LVDS6 |
PAT_PRBS_
LVDS7 |
PAT_PRBS_
LVDS8 |
PAT_LVDS5 | PAT_
LVDS6 |
||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PAT_LVDS6 | 0 | HPF_CORNER_ADC5-8 | DIG_HPF_EN_ADC5-8 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PAT_PRBS_LVDS5 | R/W | 0h | When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, the PRBS pattern on LVDS output 5 can be enabled with this bit; see the LVDS Test Pattern Mode section for further details. |
14 | PAT_PRBS_LVDS6 | R/W | 0h | When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, the PRBS pattern on LVDS output 6 can be enabled with this bit; see the LVDS Test Pattern Mode section for further details. |
13 | PAT_PRBS_LVDS7 | R/W | 0h | When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, the PRBS pattern on LVDS output 7 can be enabled with this bit; see the LVDS Test Pattern Mode section for further details. |
12 | PAT_PRBS_LVDS8 | R/W | 0h | When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, the PRBS pattern on LVDS output 8 can be enabled with this bit; see the LVDS Test Pattern Mode section for further details. |
11-9 | PAT_LVDS5 | R/W | 0h | When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, the pattern on LVDS output 5 can be programmed with these bits; see Table 33 for bit descriptions. |
8-6 | PAT_LVDS6 | R/W | 0h | When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1, the pattern on LVDS output 6 can be programmed with these bits; see Table 33 for bit descriptions. |
5 | 0 | R/W | 0h | Must write 0 |
4-1 | HPF_CORNER_ADC5-8 | R/W | 0h | When the DIG_HPF_EN_ADC5-8 bit is set to 1, the digital HPF characteristic for the corresponding ADCs can be programmed by setting the value of k with these bits.
The value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details. |
0 | DIG_HPF_EN_ADC5-8 | R/W | 0h | 0 = Digital HPF disabled for ADCs 5 to 8 (default)
1 = Enables digital HPF for ADCs 5 to 8 |