JAJSFC6C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
Mapping of the analog inputs to the LVDS outputs is shown in Table 35 for a case corresponding to a 16-input mode and a 1X data rate.
ANALOG INPUT SIGNAL | CONNECTION TO ANALOG INPUT PINS | SAMPLING INSTANT | ADC WORD | SERIAL_OUT
(Over Two Frames) |
LVDS OUTPUTS ON DOUT PINS |
---|---|---|---|---|---|
AIN1 | IN1 | t1 | ADCOUT1o | Frame 1: ADCOUT1o
Frame 2: ADCOUT1e |
DOUT1 |
t2 | ADCOUT1e | ||||
AIN2 | IN3 | t1 | ADCOUT2o | Frame 1: ADCOUT2o
Frame 2: ADCOUT2e |
DOUT2 |
t2 | ADCOUT2e | ||||
AIN3 | IN5 | t1 | ADCOUT3o | Frame 1: ADCOUT3o
Frame 2: ADCOUT3e |
DOUT3 |
t2 | ADCOUT3e | ||||
AIN4 | IN7 | t1 | ADCOUT4o | Frame 1: ADCOUT4o
Frame 2: ADCOUT4e |
DOUT4 |
t2 | ADCOUT4e | ||||
AIN5 | IN9 | t1 | ADCOUT5o | Frame 1: ADCOUT5o
Frame 2: ADCOUT5e |
DOUT5 |
t2 | ADCOUT5e | ||||
AIN6 | IN11 | t1 | ADCOUT6o | Frame 1: ADCOUT6o
Frame 2: ADCOUT6e |
DOUT6 |
t2 | ADCOUT6e | ||||
AIN7 | IN13 | t1 | ADCOUT7o | Frame 1: ADCOUT7o
Frame 2: ADCOUT7e |
DOUT7 |
t2 | ADCOUT7e | ||||
AIN8 | IN15 | t1 | ADCOUT8o | Frame 1: ADCOUT8o
Frame 2: ADCOUT8e |
DOUT8 |
t2 | ADCOUT8e | ||||
AIN9 | IN17 | t1 | ADCOUT9o | Frame 1: ADCOUT9o
Frame 2: ADCOUT9e |
DOUT9 |
t2 | ADCOUT9e | ||||
AIN10 | IN19 | t1 | ADCOUT10o | Frame 1: ADCOUT10o
Frame 2: ADCOUT10e |
DOUT10 |
t2 | ADCOUT10e | ||||
AIN11 | IN21 | t1 | ADCOUT11o | Frame 1: ADCOUT11o
Frame 2: ADCOUT11e |
DOUT11 |
t2 | ADCOUT11e | ||||
AIN12 | IN23 | t1 | ADCOUT12o | Frame 1: ADCOUT12o
Frame 2: ADCOUT12e |
DOUT12 |
t2 | ADCOUT12e | ||||
AIN13 | IN25 | t1 | ADCOUT13o | Frame 1: ADCOUT13o
Frame 2: ADCOUT13e |
DOUT13 |
t2 | ADCOUT13e | ||||
AIN14 | IN27 | t1 | ADCOUT14o | Frame 1: ADCOUT14o
Frame 2: ADCOUT14e |
DOUT14 |
t2 | ADCOUT14e | ||||
AIN15 | IN29 | t1 | ADCOUT15o | Frame 1: ADCOUT15o
Frame 2: ADCOUT15e |
DOUT15 |
t2 | ADCOUT15e | ||||
AIN16 | IN31 | t1 | ADCOUT16o | Frame 1: ADCOUT16o
Frame 2: ADCOUT16e |
DOUT16 |
t2 | ADCOUT16e |
Mapping of the analog inputs to the LVDS outputs is shown in Table 36 for a case corresponding to a 16-input mode and a 2X data rate.
ANALOG INPUT SIGNAL | CONNECTION TO ANALOG INPUT PINS | SAMPLING INSTANT | ADC WORD | SERIAL_OUT
(Over Two Frames) |
LVDS OUTPUTS ON DOUT PINS |
---|---|---|---|---|---|
AIN1 | IN1 | t1 | ADCOUT1o | Frame 1: ADCOUT1o,
ADCOUT2o Frame 2: ADCOUT1e, ADCOUT2e |
DOUT1 |
t2 | ADCOUT1e | ||||
AIN2 | IN3 | t1 | ADCOUT2o | ||
t2 | ADCOUT2e | ||||
AIN3 | IN5 | t1 | ADCOUT3o | Frame 1: ADCOUT3o,
ADCOUT4o Frame 2: ADCOUT3e, ADCOUT4e |
DOUT2 |
t2 | ADCOUT3e | ||||
AIN4 | IN7 | t1 | ADCOUT4o | ||
t2 | ADCOUT4e | ||||
AIN5 | IN9 | t1 | ADCOUT5o | Frame 1: ADCOUT5o,
ADCOUT6o Frame 2: ADCOUT5e, ADCOUT6e |
DOUT3 |
t2 | ADCOUT5e | ||||
AIN6 | IN11 | t1 | ADCOUT6o | ||
t2 | ADCOUT6e | ||||
AIN7 | IN13 | t1 | ADCOUT7o | Frame 1: ADCOUT7o,
ADCOUT8o Frame 2: ADCOUT7e, ADCOUT8e |
DOUT4 |
t2 | ADCOUT7e | ||||
AIN8 | IN15 | t1 | ADCOUT8o | ||
t2 | ADCOUT8e | ||||
AIN9 | IN17 | t1 | ADCOUT9o | Frame 1: ADCOUT9o,
ADCOUT10o Frame 2: ADCOUT9e, ADCOUT10e |
DOUT9 |
t2 | ADCOUT9e | ||||
AIN10 | IN19 | t1 | ADCOUT10o | ||
t2 | ADCOUT10e | ||||
AIN11 | IN21 | t1 | ADCOUT11o | Frame 1: ADCOUT11o,
ADCOUT12o Frame 2: ADCOUT11e, ADCOUT12e |
DOUT10 |
t2 | ADCOUT11e | ||||
AIN12 | IN23 | t1 | ADCOUT12o | ||
t2 | ADCOUT12e | ||||
AIN13 | IN25 | t1 | ADCOUT13o | Frame 1: ADCOUT13o,
ADCOUT14 Frame 2: ADCOUT13e, ADCOUT14e |
DOUT11 |
t2 | ADCOUT13e | ||||
AIN14 | IN27 | t1 | ADCOUT14o | ||
t2 | ADCOUT14e | ||||
AIN15 | IN29 | t1 | ADCOUT15o | Frame 1: ADCOUT15o,
ADCOUT16o Frame 2: ADCOUT15e, ADCOUT16e |
DOUT12 |
t2 | ADCOUT15e | ||||
AIN16 | IN31 | t1 | ADCOUT16o | ||
t2 | ADCOUT16e |
Table 35 and Table 36 illustrate that the ADCs convert the odd numbered input when operating in the 16-input mode. Each ADC can be set to convert the following even numbered input using the register control IN_CH_ADCx. The performance of the ADC may slightly degrade when IN_CH_ADCx is set to 1.
In 16-input mode, there is a one-to-one mapping between the inputs and the ADCs. The register map relative to the ADCs can therefore be mapped to the 16 channels, as shown in Table 37.
REGISTER MAP NOTATION | MAPPING TO CHANNELS IN 16-INPUT MODE | EXAMPLE |
---|---|---|
GAIN_ADCxo,
GAIN_ADCxe |
GAIN_CHANNELx | GAIN_CHANNEL1 = GAIN_ADC1o (same for GAIN_ADC1e)
(Set odd and even gains of the same ADC to the same setting) |
OFFSET_ADCxo,
OFFSET_ADCxe |
OFFSET_CHANNELx | OFFSET_CHANNEL1 = OFFSET_ADC1o (same for OFFSET_ADC1e
(Set odd and even offsets of the same ADC to the same setting) |
PDN_DIG_ADCx | PDN_DIG_CHANNELx | PDN_DIG_CHANNEL1 = PDN_DIG_ADC1 |
PDN_ANA_ADCx | PDN_ANA_CHANNELx | PDN_ANA_CHANNEL1 = PDN_ANA_ADC1 |
DIG_HPF_EN_ADCx | Mapped to 4 channels | DIG_HPF_EN_CHANNEL1-4 = DIG_HPF_EN_ADC1-4
Common setting for 4 ADCs maps to common setting for 4 channels |
HPF_CORNER_ADCx | Mapped to 4 channels | HPF_CORNER_CHANNEL1-4 = HPF_CORNER_ADC1-4
Common setting for 4 ADCs maps to common setting for 4 channels |