JAJSFC6C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | SING_CONV_
PER_OCT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM_ADC_PER_LANE | 0 | 0 | 0 | 0 | 0 | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | 0 | R/W | 0h | Must write 0 |
8 | SING_CONV_PER_OCT | R/W | 0h | 0 = Data are packed efficiently and transmitted over the link
1 = Each ADC data are packed in two octets [that is, each ADC data are transmitted as 16 bits (12-, 14-, and 16-bit mode) by the appropriate zero padding]; see the User Data Format section for further details. |
7-5 | NUM_ADC_PER_LANE | R/W | 0h | 000 = Four ADCs per lane mode: data from four ADCs are packed into a lane. Four lanes are active and four lanes are powered down.
001 = Eight ADCs per lane mode: data from eight ADCs are packed into a lane. Two lanes are active and six lanes are powered down. 100 = Two ADCs per lane mode: data from two ADCs are packed into a lane. All eight lanes are active. All other settings are invalid. |
4-0 | 0 | R/W | 0h | Must write 0 |