JAJSFC6C May   2015  – April 2018 ADS52J90

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     概略回路図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Characteristics
    7. 7.7  Timing Requirements: Signal Chain
    8. 7.8  Timing Requirements: JESD Interface
    9. 7.9  Timing Requirements: Serial Interface
    10. 7.10 Typical Characteristics
    11. 7.11 Typical Characteristics: JESD Interface
    12. 7.12 Typical Characteristics: Contour Plots
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Connection of the External Inputs to the Input Pins
      2. 8.3.2  Input Multiplexer and Sampler
      3. 8.3.3  Analog-to-Digital Converter (ADC)
      4. 8.3.4  Device Synchronization Using TX_TRIG
      5. 8.3.5  Digital Processing
        1. 8.3.5.1 Digital Offset
          1. 8.3.5.1.1 Manual Offset Correction
          2. 8.3.5.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
          3. 8.3.5.1.3 Digital Averaging
          4. 8.3.5.1.4 Digital Gain
          5. 8.3.5.1.5 Digital HPF
      6. 8.3.6  Data Formatting
      7. 8.3.7  Serializer and LVDS Interface
      8. 8.3.8  LVDS Buffers
      9. 8.3.9  JESD204B Interface
        1. 8.3.9.1 Overview
        2. 8.3.9.2 Link Configuration
        3. 8.3.9.3 JESD Version and Subclass
        4. 8.3.9.4 Transport Layer
          1. 8.3.9.4.1 User Data Format
          2. 8.3.9.4.2 Transport Layer Test Patterns
        5. 8.3.9.5 Scrambler
        6. 8.3.9.6 Data Link Layer
          1. 8.3.9.6.1 Code Group Synchronization (CGS)
          2. 8.3.9.6.2 Initial Lane Alignment (ILA)
          3. 8.3.9.6.3 Lane and Frame Alignment Monitoring
          4. 8.3.9.6.4 Link Layer Test Modes
        7. 8.3.9.7 Deterministic Latency
          1. 8.3.9.7.1 Synchronization Using SYNC~ and SYSREF
          2. 8.3.9.7.2 Latency
          3. 8.3.9.7.3 Multiframe Size
        8. 8.3.9.8 JESD Physical Layer
          1. 8.3.9.8.1 CML Buffer
          2. 8.3.9.8.2 Jitter Considerations
      10. 8.3.10 Interfacing SYNC~ and SYSREF Between the FPGA and ADCs
      11. 8.3.11 Clock Input
      12. 8.3.12 Analog Input and Driving Circuit
        1. 8.3.12.1 Signal Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Modes
      2. 8.4.2 ADC Resolution Modes
      3. 8.4.3 LVDS and JESD Interface Modes
      4. 8.4.4 LVDS Serialization and Output Data Rate Modes
      5. 8.4.5 Power Modes
      6. 8.4.6 LVDS Test Pattern Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Operation
        1. 8.5.1.1 Serial Register Write Description
        2. 8.5.1.2 Register Readout
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing with the 16-Input Mode
        2. 9.2.2.2 Designing with the 32-Input Mode
        3. 9.2.2.3 Designing with the 8-Input Mode
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Power Supply, Grounding, and Bypassing
    2. 11.2 Layout Guidelines
    3. 11.3 Layout Example
  12. 12Register Map
    1. 12.1 ADC Registers
      1. 12.1.1 Description of Registers
        1. 12.1.1.1  Register 0h (address = 0h)
          1. Table 47. Register 0h Field Descriptions
        2. 12.1.1.2  Register 1h (address = 1h)
          1. Table 48. Register 1h Field Descriptions
        3. 12.1.1.3  Register 2h (address = 2h)
          1. Table 51. Register 2h Field Descriptions
        4. 12.1.1.4  Register 3h (address = 3h)
          1. Table 53. Register 3h Field Descriptions
        5. 12.1.1.5  Register 4h (address = 4h)
          1. Table 54. Register 4h Field Descriptions
        6. 12.1.1.6  Register 5h (address = 5h)
          1. Table 55. Register 5h Field Descriptions
        7. 12.1.1.7  Register 7h (address = 7h)
          1. Table 56. Register 7h Field Descriptions
        8. 12.1.1.8  Register 8h (address = 8h)
          1. Table 57. Register 8h Field Descriptions
        9. 12.1.1.9  Register Ah (address = Ah)
          1. Table 58. Register Ah Field Descriptions
        10. 12.1.1.10 Register Bh (address = Bh)
          1. Table 59. Register Bh Field Descriptions
        11. 12.1.1.11 Register Dh (address = Dh)
          1. Table 60. Register Dh Field Descriptions
        12. 12.1.1.12 Register Eh (address = Eh)
          1. Table 61. Register Eh Field Descriptions
        13. 12.1.1.13 Register Fh (address = Fh)
          1. Table 62. Register Fh Field Descriptions
        14. 12.1.1.14 Register 10h (address = 10h)
          1. Table 63. Register 10h Field Descriptions
        15. 12.1.1.15 Register 11h (address = 11h)
          1. Table 64. Register 11h Field Descriptions
        16. 12.1.1.16 Register 12h (address = 12h)
          1. Table 65. Register 12h Field Descriptions
        17. 12.1.1.17 Register 13h (address = 13h)
          1. Table 66. Register 13h Field Descriptions
        18. 12.1.1.18 Register 14h (address = 14h)
          1. Table 67. Register 14h Field Descriptions
        19. 12.1.1.19 Register 15h (address = 15h)
          1. Table 68. Register 15h Field Descriptions
        20. 12.1.1.20 Register 17h (address = 17h)
          1. Table 69. Register 17h Field Descriptions
        21. 12.1.1.21 Register 18h (address = 18h)
          1. Table 70. Register 18h Field Descriptions
        22. 12.1.1.22 Register 19h (address = 19h)
          1. Table 71. Register 19h Field Descriptions
        23. 12.1.1.23 Register 1Ah (address = 1Ah)
          1. Table 72. Register 1Ah Field Descriptions
        24. 12.1.1.24 Register 1Bh (address = 1Bh)
          1. Table 73. Register 1Bh Field Descriptions
        25. 12.1.1.25 Register 1Ch (address = 1Ch)
          1. Table 74. Register 1Ch Field Descriptions
        26. 12.1.1.26 Register 1Dh (address = 1Dh)
          1. Table 75. Register 1Dh Field Descriptions
        27. 12.1.1.27 Register 1Eh (address = 1Eh)
          1. Table 76. Register 1Eh Field Descriptions
        28. 12.1.1.28 Register 1Fh (address = 1Fh)
          1. Table 77. Register 1Fh Field Descriptions
        29. 12.1.1.29 Register 20h (address = 20h)
          1. Table 78. Register 20h Field Descriptions
        30. 12.1.1.30 Register 21h (offset = 21h)
          1. Table 79. Register 21h Field Descriptions
        31. 12.1.1.31 Register 23h (register = 23h)
          1. Table 80. Register 23h Field Descriptions
        32. 12.1.1.32 Register 24h (address = 24h)
          1. Table 81. Register 24h Field Descriptions
        33. 12.1.1.33 Register 25h (address = 25h)
          1. Table 82. Register 25h Field Descriptions
        34. 12.1.1.34 Register 26h (address = 26h)
          1. Table 83. Register 26h Field Descriptions
        35. 12.1.1.35 Register 27h (address = 27h)
          1. Table 84. Register 27h Field Descriptions
        36. 12.1.1.36 Register 28h (address = 28h)
          1. Table 85. Register 28h Field Descriptions
        37. 12.1.1.37 Register 29h (address = 29h)
          1. Table 86. Register 29h Field Descriptions
        38. 12.1.1.38 Register 2Ah (address = 2Ah)
          1. Table 87. Register 2Ah Field Descriptions
        39. 12.1.1.39 Register 2Bh (address = 2Bh)
          1. Table 88. Register 2Bh Field Descriptions
        40. 12.1.1.40 Register 2Ch (address = 2Ch)
          1. Table 89. Register 2Ch Field Descriptions
        41. 12.1.1.41 Register 2Dh (address = 2Dh)
          1. Table 90. Register 2Dh Field Descriptions
        42. 12.1.1.42 Register 2Fh (address = 2Fh)
          1. Table 91. Register 2Fh Field Descriptions
        43. 12.1.1.43 Register 30h (address = 30h)
          1. Table 92. Register 30h Field Descriptions
        44. 12.1.1.44 Register 31h (address = 31h)
          1. Table 93. Register 31h Field Descriptions
        45. 12.1.1.45 Register 32h (address = 32h)
          1. Table 94. Register 32h Field Descriptions
        46. 12.1.1.46 Register 33h (address = 33h)
          1. Table 95. Register 33h Field Descriptions
        47. 12.1.1.47 Register 34h (address = 34h)
          1. Table 96. Register 34h Field Descriptions
        48. 12.1.1.48 Register 35h (address = 35h)
          1. Table 97. Register 35h Field Descriptions
        49. 12.1.1.49 Register 36h (address = 36h)
          1. Table 98. Register 36h Field Descriptions
        50. 12.1.1.50 Register 37h (address = 37h)
          1. Table 99. Register 37h Field Descriptions
        51. 12.1.1.51 Register 38h (address = 38h)
          1. Table 100. Register 38h Field Descriptions
        52. 12.1.1.52 Register 39h (address = 39h)
          1. Table 101. Register 39h Field Descriptions
        53. 12.1.1.53 Register 3Bh (address = 3Bh)
          1. Table 102. Register 3Bh Field Descriptions
        54. 12.1.1.54 Register 3Ch (address = 3Ch)
          1. Table 103. Register 3Ch Field Descriptions
        55. 12.1.1.55 Register 43h (address = 43h)
          1. Table 104. Register 43h Field Descriptions
    2. 12.2 JESD Serial Interface Registers
      1. 12.2.1 Description of JESD Serial Interface Registers
        1. 12.2.1.1  Register 70 (address = 46h)
          1. Table 106. Register 70 Field Descriptions
        2. 12.2.1.2  Register 73 (address = 49h)
          1. Table 107. Register 73 Field Descriptions
        3. 12.2.1.3  Register 74 (address = 4Ah)
          1. Table 108. Register 74 Field Descriptions
        4. 12.2.1.4  Register 75 (address = 4Bh)
          1. Table 109. Register 75 Field Descriptions
        5. 12.2.1.5  Register 77 (address = 4Dh)
          1. Table 110. Register 77 Field Descriptions
        6. 12.2.1.6  Register 80 (address = 50h)
          1. Table 111. Register 80 Field Descriptions
        7. 12.2.1.7  Register 81 (address = 51h)
          1. Table 112. Register 81 Field Descriptions
        8. 12.2.1.8  Register 82 (address = 52h)
          1. Table 113. Register 82 Field Descriptions
        9. 12.2.1.9  Register 83 (address = 53h)
          1. Table 114. Register 83 Field Descriptions
        10. 12.2.1.10 Register 85 (address = 55h)
          1. Table 115. Register 85 Field Descriptions
        11. 12.2.1.11 Register 115 (address = 73h)
          1. Table 116. Register 115 Field Descriptions
        12. 12.2.1.12 Register 116 (address = 74h)
          1. Table 117. Register 116 Field Descriptions
        13. 12.2.1.13 Register 117 (address = 75h)
          1. Table 118. Register 117 Field Descriptions
        14. 12.2.1.14 Register 118 (address = 76h)
          1. Table 119. Register 118 Field Descriptions
        15. 12.2.1.15 Register 119 (address = 77h)
          1. Table 120. Register 119 Field Descriptions
        16. 12.2.1.16 Register 120 (address = 78h)
          1. Table 121. Register 120 Field Descriptions
        17. 12.2.1.17 Register 134 (address = 86h)
          1. Table 122. Register 134 Field Descriptions
        18. 12.2.1.18 Register 135 (address = 87h)
          1. Table 123. Register 135 Field Descriptions
        19. 12.2.1.19 Register 136 (address = 88h)
          1. Table 124. Register 136 Field Descriptions
        20. 12.2.1.20 Register 137 (address = 89h)
          1. Table 125. Register 137 Field Descriptions
        21. 12.2.1.21 Register 138 (address = 8Ah)
          1. Table 126. Register 138 Field Descriptions
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 コミュニティ・リソース
    3. 13.3 商標
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • ZZE|198
サーマルパッド・メカニカル・データ
発注情報

8.3.9.4.1 User Data Format

The interface can be configured to operate in 2, 4, or 8 lane modes (L = 2, 4, or 8). Depending on the number of lanes used, the data from the 16 ADCs comes out in the different lanes as shown in Table 17.

Table 17. Lane Mapping to CML Pins(1)

DEFAULT LANE ID MAPPING TO THE PINS 2 ADCS PER LANE
(8-Lane Mode)(2) 		4 ADCS PER LANE
(4-Lane Mode)(2) 		8 ADCS PER LANE
(2-Lane Mode)(2)
1 CML1_OUTP-CML1_OUTM ADC1, ADC2 ADC1…ADC4 ADC1…ADC8
2 CML2_OUTP-CML2_OUTM ADC3, ADC4 — —
3 CML3_OUTP-CML3_OUTM ADC5, ADC6 ADC5…ADC8 —
4 CML4_OUTP-CML4_OUTM ADC7, ADC8 — —
5 CML5_OUTP-CML5_OUTM ADC9, ADC10 ADC9…ADC12 ADC9…ADC16
6 CML6_OUTP-CML6_OUTM ADC11, ADC12 — —
7 CML7_OUTP-CML7_OUTM ADC13, ADC14 ADC13…ADC16 —
8 CML8_OUTP-CML8_OUTM ADC15, ADC16 — —
(1) More accurately, ADC1…ADC16 corresponds to CML_IN1…CML_IN16 as illustrated in Figure 72.
(2) Determined by the NUM_ADC_PER_LANE register control.

The unused lanes are automatically powered down.

The device supports several combinations of ADC resolutions and number of lanes. There are no control bits or control words (CF = 0). The device has two modes of data packing: normal packing mode and single converter per octet mode. The packing mode can be chosen using the SING_CONV_PER_OCT register control. The number of ADCs per lane can be programmed to 8, 4, or 2 using the NUM_ADC_PER_LANE register control. The number of ADCs per lane automatically determines the value of L (the number of lanes). The values of N’ and F for the different modes are described in Table 18.

Table 18. Different JESD204B Interface Modes of Operation

NUMBER OF ADCS PER LANE, NAL(1) SER_DATA_
RATE, NSER(1)(5) (Bits)		 ADC_RES, NRES(1)
(Bits)		 L(2)
(Lanes)		 N(2)
(Resolution of ADC Word Input to the JESD204B Transmitter)		 NORMAL PACKING MODE(1) SINGLE CONVERTER PER OCTET MODE(1)
N'(2)
(Total Number of Bits)		 F(2)
(Octets per Frame)		 N'(2)
(Total Number of Bits)		 F(2)
(Octets per Frame)
8 10, 12, 14, 16 10, 12, 14, 16 2 ADC_RES SER_DATA_
RATE (6) 		SER_DATA_
RATE		 16 16(4)
4 10, 12, 14, 16 10, 12, 14, 16 4 ADC_RES SER_DATA_
RATE(6) 		SER_DATA_
RATE/2		 16 8(4)
2 10 10 8 ADC_RES 12 3(3) 16 4(4)
12 10, 12 ADC_RES 12 3 16 4(4)
14 10, 12, 14 ADC_RES 16 4(3) 16 4(4)
16 10, 12, 14, 16 ADC_RES 16 4 16 4(4)
(1) Value or mode is set by programming the appropriate registers.
(2) Automatically calculated and set by the device.
(3) Each ADC sample is broken into nibbles; incomplete nibbles are completed using zeros as tail bits.
(4) Each ADC sample is broken into two octets; the incomplete octet is completed using zeros as tail bits.
(5) SER_DATA_RATE must be greater than or equal to ADC_RES.
(6) When SER_DATA_RATE > ADC_RES, then each ADC word is additionally padded with the (SER_DATA_RATE – ADC_RES) number of zeros on the LSB side to create the‘JESD ADC word. Each JESD ADC word is broken up into nibbles. Incomplete nibbles (if any) are stuffed with the starting bits of the subsequent JESD ADC word for maximum data packing.

The data packing modes are described in Table 19 to Table 24 for different modes of operation. Lane 1 is used for illustration purposes in these tables.

Table 19. Data Packing in Normal Packing Mode for NAL = 8 and NRES = NSER(1)

OCTET NRES = 10, NSER = 10 NRES = 12, NSER = 12 NRES = 14, NSER = 14 NRES = 16, NSER = 16
NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2
1 ADC1[9:6] ADC1[5:2] ADC1[11:8] ADC1[7:4] ADC1[13:10] ADC1[9:6] ADC1[15:12] ADC1[11:8]
2 ADC1[1:0],
ADC2[9:8]		 ADC2[7:4] ADC1[3:0] ADC2[11:8] ADC1[5:2] ADC1[1:0],
ADC2[13:12]		 ADC1[7:4] ADC1[3:0]
3 ADC2[3:0] ADC3[9:6] ADC2[7:4] ADC2[3:0] ADC2[11:8] ADC2[7:4] ADC2[15:12] ADC2[11:8]
4 ADC3[5:2] ADC3[1:0],
ADC4[9:8]		 ADC3[11:8] ADC3[7:4] ADC2[3:0] ADC3[13:10] ADC2[7:4] ADC2[3:0]
5 ADC4[7:4] ADC4[3:0] ADC3[3:0] ADC4[11:8] ADC3[9:6] ADC3[5:2] ADC3[15:12] ADC3[11:8]
6 ADC5[9:6] ADC5[5:2] ADC4[7:4] ADC4[3:0] ADC3[1:0],
ADC4[13:12]		 ADC4[11:8] ADC3[7:4] ADC3[3:0]
7 ADC5[1:0],
ADC6[9:8]		 ADC6[7:4] ADC5[11:8] ADC5[7:4] ADC4[7:4] ADC4[3:0] ADC4[15:12] ADC4[11:8]
8 ADC6[3:0] ADC7[9:6] ADC5[3:0] ADC6[11:8] ADC5[13:10] ADC5[9:6] ADC4[7:4] ADC4[3:0]
9 ADC7[5:2] ADC7[1:0],
ADC8[9:8]		 ADC6[7:4] ADC6[3:0] ADC5[5:2] ADC5[1:0],
ADC6[13:12]		 ADC5[15:12] ADC5[11:8]
10 ADC7[7:4] ADC8[3:0] ADC7[11:8] ADC7[7:4] ADC6[11:8] ADC6[7:4] ADC5[7:4] ADC5[3:0]
11 — — ADC7[3:0] ADC8[11:8] ADC6[3:0] ADC7[13:10] ADC6[15:12] ADC6[11:8]
12 — — ADC8[7:4] ADC8[3:0] ADC7[9:6] ADC7[5:2] ADC6[7:4] ADC6[3:0]
13 — — — — ADC7[1:0],
ADC8[13:12]		 ADC8[11:8] ADC7[15:12] ADC7[11:8]
14 — — — — ADC8[7:4] ADC8[3:0] ADC7[7:4] ADC7[3:0]
15 — — — — — — ADC8[15:12] ADC8[11:8]
16 — — — — — — ADC8[7:4] ADC8[3:0]
(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in Table 17.

Table 20. Data Packing in Normal Packing Mode for NAL = 8 and NSER> NRES(1)

OCTET NRES = 10, NSER = 12 NRES = 12, NSER = 14 NRES = 14, NSER = 16
NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2
1 ADC1[9:6] ADC1[5:2] ADC1[11:8] ADC1[7:4] ADC1[13:10] ADC1[9:6]
2 ADC1[1:0], 00 ADC2[9:6] ADC1[3:0] 00,ADC2[11:10] ADC1[5:2] ADC1[1:0], 00
3 ADC2[5:2] ADC2[1:0], 00 ADC2[9:6] ADC2[5:2] ADC2[13:10] ADC2[9:6]
4 ADC3[9:6] ADC3[5:2] ADC2[1:0],00 ADC3[11:8] ADC2[5:2] ADC2[1:0], 00
5 ADC3[1:0], 00 ADC4[9:6] ADC3[7:4] ADC3[3:0] ADC3[13:10] ADC3[9:6]
6 ADC4[5:2] ADC4[1:0], 00 00,ADC4[11:10] ADC4[9:6] ADC3[5:2] ADC3[1:0], 00
7 ADC5[9:6] ADC5[5:2] ADC4[5:2] ADC4[1:0],00 ADC4[13:10] ADC4[9:6]
8 ADC5[1:0], 00 ADC6[9:6] ADC5[11:8] ADC5[7:4] ADC4[5:2] ADC4[1:0], 00
9 ADC6[5:2] ADC6[1:0], 00 ADC5[3:0] 00,ADC6[11:10] ADC5[13:10] ADC5[9:6]
10 ADC7[9:6] ADC7[5:2] ADC6[9:6] ADC6[5:2] ADC5[5:2] ADC5[1:0], 00
11 ADC7[1:0], 00 ADC8[9:6] ADC6[1:0],00 ADC7[11:8] ADC6[13:10] ADC6[9:6]
12 ADC8[5:2] ADC8[1:0], 00 ADC7[7:4] ADC7[3:0] ADC6[5:2] ADC6[1:0], 00
13 — — 00,ADC8[11:10] ADC8[9:6] ADC7[13:10] ADC7[9:6]
14 — — ADC8[5:2] ADC8[1:0],00 ADC7[5:2] ADC7[1:0], 00
15 — — — — ADC8[13:10] ADC8[9:6]
16 — — — — ADC8[5:2] ADC8[1:0], 00
(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in Table 17.

Table 21. Data Packing in Normal Packing Mode for NAL = 4 and NRES = NSER(1)

OCTET NRES = 10, NSER = 10 NRES = 12, NSER = 12 NRES = 14, NSER = 14 NRES = 16, NSER = 16
NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2
1 ADC1[9:6] ADC1[5:2] ADC1[11:8] ADC1[7:4] ADC1[13:10] ADC1[9:6] ADC1[15:12] ADC1[11:8]
2 ADC1[1:0],
ADC2[9:8]		 ADC2[7:4] ADC1[3:0] ADC2[11:8] ADC1[5:2] ADC1[1:0],
ADC2[13:12]		 ADC1[7:4] ADC1[3:0]
3 ADC2[3:0] ADC3[9:6] ADC2[7:4] ADC2[3:0] ADC2[11:8] ADC2[7:4] ADC2[15:12] ADC2[11:8]
4 ADC3[5:2] ADC3[1:0],
AD4[9:8]		 ADC3[11:8] ADC3[7:4] ADC2[3:0] ADC3[13:10] ADC2[7:4] ADC2[3:0]
5 ADC4[7:4] ADC4[3:0] ADC3[3:0] ADC4[11:8] ADC3[9:6] ADC3[5:2] ADC3[15:12] ADC3[11:8]
6 — — ADC4[7:4] ADC4[3:0] ADC3[1:0],
ADC4[13:12]		 ADC4[11:8] ADC3[7:4] ADC3[3:0]
7 — — — — ADC4[7:4] ADC4[3:0] ADC4[15:12] ADC4[11:8]
8 — — — — — — ADC4[7:4] ADC4[3:0]
(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in Table 17.

Table 22. Data Packing in Normal Packing Mode for NAL = 4 and NSER> NRES(1)

OCTET NRES = 10, NSER = 12 NRES = 12, NSER = 14 NRES = 14, NSER = 16
NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2
1 ADC1[9:6] ADC1[5:2] ADC1[11:8] ADC1[7:4] ADC1[13:10] ADC1[9:6]
2 ADC1[1:0], 00 ADC2[9:6] ADC1[3:0] 00,ADC2[11:10] ADC1[5:2] ADC1[1:0], 00
3 ADC2[5:2] ADC2[1:0], 00 ADC2[9:6] ADC2[5:2] ADC2[13:10] ADC2[9:6]
4 ADC3[9:6] ADC3[5:2] ADC2[1:0],00 ADC3[11:8] ADC2[5:2] ADC2[1:0], 00
5 ADC3[1:0], 00 ADC4[9:6] ADC3[7:4] ADC3[3:0] ADC3[13:10] ADC3[9:6]
6 ADC4[5:2] ADC4[1:0], 00 00,ADC4[11:10] ADC4[9:6] ADC3[5:2] ADC3[1:0], 00
7 — — ADC4[5:2] ADC4[1:0],00 ADC4[13:10] ADC4[9:6]
8 — — — — ADC4[5:2] ADC4[1:0], 00
(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in Table 17.

Table 23. Data Packing in Normal Packing Mode for NAL = 2(1)

OCTET NRES = 10, NSER = 10 or 12 NRES = 12, NSER = 12 NRES = 14, NSER = 14 or 16 NRES = 16, NSER = 16
NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2
1 ADC1[9:6] ADC1[5:2] ADC1[11:8] ADC1[7:4] ADC1[13:10] ADC1[9:6] ADC1[15:12] ADC1[11:8]
2 ADC1[1:0], 00 ADC2[9:6] ADC1[3:0] ADC2[11:8] ADC1[5:2] ADC1[1:0], 00 ADC1[7:4] ADC1[3:0]
3 ADC2[5:2] ADC3[1:0], 00 ADC2[7:4] ADC2[3:0] ADC2[13:10] ADC2[9:6] ADC2[15:12] ADC2[11:8]
4 — — — — ADC2[5:2] ADC2[1:0], 00 ADC2[7:4] ADC2[3:0]
(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in Table 17.

Table 24. Data Packing in Single Converter per Octet Packing Mode for NAL = 8 (Independent of NSER)(1)(2)

OCTET NRES = 10 NRES = 12 NRES = 14 NRES = 16, NSER = 16
NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2 NIBBLE 1 NIBBLE 2
1 ADC1[9:6] ADC1[5:2] ADC1[11:8] ADC1[7:4] ADC1[13:10] ADC1[9:6] ADC1[15:12] ADC1[11:8]
2 ADC1[1:0], 00 0000 ADC1[3:0] 0000 ADC1[5:2] ADC1[1:0], 00 ADC1[7:4] ADC1[3:0]
3 ADC2[9:6] ADC2[5:2] ADC2[11:8] ADC2[7:4] ADC2[13:10] ADC2[9:6] ADC2[15:12] ADC2[11:8]
4 ADC2[1:0], 00 0000 ADC2[3:0] 0000 ADC2[5:2] ADC2[1:0], 00 ADC2[7:4] ADC2[3:0]
5 ADC3[9:6] ADC3[5:2] ADC3[11:8] ADC3[7:4] ADC3[13:10] ADC3[9:6] ADC3[15:12] ADC3[11:8]
6 ADC3[1:0], 00 0000 ADC3[3:0] 0000 ADC3[5:2] ADC3[1:0], 00 ADC3[7:4] ADC3[3:0]
7 ADC4[9:6] ADC4[5:2] ADC4[11:8] ADC4[7:4] ADC4[13:10] ADC4[9:6] ADC4[15:12] ADC4[11:8]
8 ADC4[1:0], 00 0000 ADC4[3:0] 0000 ADC4[5:2] ADC4[1:0], 00 ADC4[7:4] ADC4[3:0]
9 ADC5[9:6] ADC5[5:2] ADC5[11:8] ADC5[7:4] ADC5[13:10] ADC5[9:6] ADC5[15:12] ADC5[11:8]
10 ADC5[1:0], 00 0000 ADC5[3:0] 0000 ADC5[5:2] ADC5[1:0], 00 ADC5[7:4] ADC5[3:0]
11 ADC6[9:6] ADC6[5:2] ADC6[11:8] ADC6[7:4] ADC6[13:10] ADC6[9:6] ADC6[15:12] ADC6[11:8]
12 ADC6[1:0], 00 0000 ADC6[3:0] 0000 ADC6[5:2] ADC6[1:0], 00 ADC6[7:4] ADC6[3:0]
13 ADC7[9:6] ADC7[5:2] ADC7[11:8] ADC7[7:4] ADC7[13:10] ADC7[9:6] ADC7[15:12] ADC7[11:8]
14 ADC7[1:0], 00 0000 ADC7[3:0] 0000 ADC7[5:2] ADC7[1:0], 00 ADC7[7:4] ADC7[3:0]
15 ADC8[9:6] ADC8[5:2] ADC8[11:8] ADC8[7:4] ADC8[13:10] ADC8[9:6] ADC8[15:12] ADC8[11:8]
16 ADC8[1:0], 00 0000 ADC8[3:0] 0000 ADC8[5:2] ADC8[1:0], 00 ADC8[7:4] ADC8[3:0]
(1) For NAL = 4, use the first eight octets. For NAL = 2, use the first four octets.
(2) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in Table 17.

Tail bits (in modes where applicable) are set to 0. There is no option for a pseudo-random generator for generating the tail bits. When a converter is powered down, the corresponding sample is replaced by a dummy sample that corresponds to all zeros. There is no option for a pseudo-random generator for generating the dummy samples. The value S (number of samples per ADC per frame minus 1) is always 0 and HD mode is not supported.