JAJSOH4 august   2023 DRV8213

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
    7. 7.7 Typical Operating Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 External Components
    4. 8.4 Feature Description
      1. 8.4.1 Bridge Control
      2. 8.4.2 Current Sense and Regulation (IPROPI)
        1. 8.4.2.1 Current Sensing and Current Mirror Gain Selection
        2. 8.4.2.2 Current Regulation
      3. 8.4.3 Hardware Stall Detection
      4. 8.4.4 Protection Circuits
        1. 8.4.4.1 Overcurrent Protection (OCP)
        2. 8.4.4.2 Thermal Shutdown (TSD)
        3. 8.4.4.3 VM Undervoltage Lockout (UVLO)
    5. 8.5 Device Functional Modes
      1. 8.5.1 Active Mode
      2. 8.5.2 Low-Power Sleep Mode
      3. 8.5.3 Fault Mode
    6. 8.6 Pin Diagrams
      1. 8.6.1 Logic-Level Inputs
      2. 8.6.2 Tri-Level Input
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Brushed DC Motor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Voltage
          2. 9.2.1.2.2 Motor Current
        3. 9.2.1.3 Stall Detection
          1. 9.2.1.3.1 Detailed Design Procedure
            1. 9.2.1.3.1.1 Hardware Stall Detection Application Description
              1. 9.2.1.3.1.1.1 Hardware Stall Detection Timing
              2. 9.2.1.3.1.1.2 Hardware Stall Threshold Selection
            2. 9.2.1.3.1.2 Software Stall Detection Application Description
              1. 9.2.1.3.1.2.1 Software Stall Detection Timing
              2. 9.2.1.3.1.2.2 Software Stall Threshold Selection
        4. 9.2.1.4 Application Curves
        5. 9.2.1.5 Thermal Performance
          1. 9.2.1.5.1 Steady-State Thermal Performance
          2. 9.2.1.5.2 Transient Thermal Performance
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1 Active Mode

After the supply voltage on the VM pin (DSG package) or VCC pin (RTE package) has crossed the rising undervoltage threshold VUVLO, the INx pins are in a state other than IN1 = 0 & IN2 = 0, and tWAKE has elapsed, the device enters active mode. In this mode, the full-bridge, charge pump, and internal logic are active and the device is ready to receive inputs.

In the RTE package, when VVCC < VVM, the DRV8213 draws active current from the VM pin rather than the VCC pin (IVM). During this operating condition, IVCC is typically less than 500 nA. When VVCC > VVM, the device draws active current from the VCC pin, and the VM pin will only draw current required by the load. When VVCC = VVM, the active current may be drawn from either supply pin. The active current is typically less than 1.9 mA.