DLPU100A May   2020  – April 2024 DLP3021-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Purpose and Scope
  5. 2FPGA Pin Configuration and Functions
    1. 2.1 DMD Interface
    2. 2.2 Light Control
    3. 2.3 Communication
    4. 2.4 Support
    5. 2.5 FPGA Dedicated Pins
    6. 2.6 Power and Ground
    7. 2.7 Unused Pins
  6. 3Specifications
    1. 3.1 Recommended Operating Conditions
    2. 3.2 FPGA Power Consumption
    3. 3.3 Host SPI Interface Timing
    4. 3.4 Power Supply and Reset Timing
      1. 3.4.1 Power-Up Timing
      2. 3.4.2 Power-Down Timing
      3. 3.4.3 Brownout Detection
    5. 3.5 DMD Interface Timing
    6. 3.6 Flash Memory Interface Timing
    7. 3.7 Reference Clock Timing
    8. 3.8 I2C Interface Timing
  7. 4Feature Descriptions
    1. 4.1 Video Control
      1. 4.1.1 Video Options
      2. 4.1.2 Example 1: Display a Static Image
      3. 4.1.3 Example 2: Display 1 Video Repeatedly
      4. 4.1.4 Example 3: Display Two Videos Then Stop
      5. 4.1.5 Example 4: Display a Video Once and Then Display an Image Forever
      6. 4.1.6 Example 5: Display 3+ Videos/Images Seamlessly
    2. 4.2 Temperature Measurements
    3. 4.3 PWM Outputs
    4. 4.4 Host IRQ Interrupt Signal
    5. 4.5 Video and Image Compression
  8. 5Layout
  9. 6Host Command Protocol
    1. 6.1 SPI Specifications
    2. 6.2 SPI Write Command
    3. 6.3 SPI Read Command
  10. 7FPGA Register Definitions
  11. 8Revision History

7 FPGA Register Definitions

This section defines the FPGA registers that can be accessed over SPI.

Table 7-1 lists the memory-mapped registers for the device registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations and the register contents should not be modified.

Table 7-1 FPGA SPI Registers
Address Acronym Register Name Section
0x0 FPGA_INTERRUPT_CLEAR FPA Interrupt Clear Go
0x4 FPGA_INTERRUPT_SET FPGA Interrupt set Go
0x8 FPGA_INTERRUPT_ENABLE FPGA Interrupt enable Go
0xC FPGA_MAIN_STATUS TI internal use. Read/Write behavior is not defined.
0x10 FPGA_VERSION FPGA Version Go
0x14 FPGA_CONTROL TI internal use. Read/Write behavior is not defined.
0x20 FMT_FLIP Format flip Go
0x24 FMT_CONTROL TI internal use. Read/Write behavior is not defined.
0x28 FMT_CMB_STATUS. TI internal use. Read/Write behavior is not defined.
0x2C FMT_FRB_STATUS TI internal use. Read/Write behavior is not defined.
0x30 RSC_SW_DMD_UNPARK TI internal use. Read/Write behavior is not defined.
0x34 RSC_PARK_WAVEFORM_CTRL TI internal use. Read/Write behavior is not defined.
0x38 RSC_UNUSED TI internal use. Read/Write behavior is not defined.
0x3C RSC_MISC_CONTROL TI internal use. Read/Write behavior is not defined.
0x40 RSC_SEQ_CONTROL TI internal use. Read/Write behavior is not defined.
0x44 RSC_SEQBUF_SELECT Sequence Buffer Select Go
0x50 PWM_CONTROL PWM Control Go
0x60 VCM_FRAME_RATE Frame Rate Go
0x64 VCM_START_ADDR1 Video 1 start address Go
0x68 VCM_CONFIG1 Video configuration 1 Go
0x6C VCM_START_ADDR2 Video 2 start address Go
0x70 VCM_CONFIG2 Video configuration 2 Go
0x74 VCM_CONTROL Video control Go
0x78 VCM_STATUS Video Status Go
0x7C VCM_SEQABORT TI internal use. Read/Write behavior is not defined.
0x80 VCM_TMSEL TI internal use. Read/Write behavior is not defined.
0x90 TMP_CTRL(1) Temperature control Go
0x94 TMP_STATUS(1) Temperature Status Go
0x98 TMP_REMOTE_TEMP(1) Remote Temperature Measurement Go
0x9C TMP_LOCAL_TEMP(1) Local Temperature Measurement Go
0xDC DESTOP_TIMEOUT_DEBUG_INFO_REG TI internal use. Read/Write behavior is not defined.
0xE0 DESTOP_MBOX0_SAPTR_REG TI internal use. Read/Write behavior is not defined.
0xE4 DESTOP_MBOX0_CTRL_REG TI internal use. Read/Write behavior is not defined.
0xF0 DESTOP_MBOX0_DATA_REG TI internal use. Read/Write behavior is not defined.
0x100 DESTOP_MBOX1_SAPTR_REG TI internal use. Read/Write behavior is not defined.
0x104 DESTOP_MBOX1_CTRL_REG TI internal use. Read/Write behavior is not defined.
0x110 DESTOP_MBOX1_DATA_REG TI internal use. Read/Write behavior is not defined.
(1) This register is not applicable to the DLP2021-Q1.

Complex bit access types are encoded to fit into small table cells. Section 7 shows the codes that are used for access types in this section.

Table 7-2 Device Access Type Codes
ACCESS TYPE CODE DESCRIPTION
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.1 FPGA_INTERRUPT_CLEAR Register (Address = 0x0) [reset = 0x0]

FPGA_INTERRUPT_CLEAR is shown in Section 7.

Return to Summary Table.

Write 1 to any bit to clear the interrupt event.

Table 7-3 FPGA_INTERRUPT_CLEAR Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-5 RESERVED R 0x0 Reserved
4 VID_CONFIG_COMP_IRQ R/W 0x0 Video configuration completed including all requested loops. This triggers once after all loops of a video complete. If both video configurations are requested to be used, it will trigger after each configuration completes.
3 VID_LOOP_COMP_IRQ R/W 0x0 Video loop completed. If multiple loops of a video are requested, this interrupt triggers after each completed loop.
2 BROWNOUT_IRQ R/W 0x0 Brownout detected
1 INIT_DONE_IRQ R/W 0x0 Initialization done
0 RESERVED R 0x0 Reserved

7.2 FPGA_INTERRUPT_SET Register (Address = 0x4) [reset = 0x0]

FPGA_INTERRUPT_SET is shown in Table 7-4.

Return to Summary Table.

Read the status of interrupt events.

Table 7-4 FPGA_INTERRUPT_SET Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-5 RESERVED R 0x0 Reserved
4 VID_CONFIG_COMP_IRQ R/W 0x0 Video configuration completed including all requested loops. This triggers once after all loops of a video complete. If both video configurations are requested to be used, it will trigger after each configuration completes.
3 VID_LOOP_COMP_IRQ R/W 0x0 Video loop completed. If multiple loops of a video are requested, this interrupt triggers after each completed loop.
2 BROWNOUT_IRQ R/W 0x0 Brownout detected
1 INIT_DONE_IRQ R/W 0x0 Initialization done
0 RESERVED R 0x0 Reserved

7.3 FPGA_INTERRUPT_ENABLE Register (Address = 0x8) [reset = 0x0]

FPGA_INTERRUPT_ENABLE is shown in Table 7-5.

Return to Summary Table.

Interrupt event mask. Write 1 to any bit to enable that interrupt event to set HOST IRQ high.

Table 7-5 FPGA_INTERRUPT_ENABLE Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-5 RESERVED R 0x0 Reserved
4 VID_CONFIG_COMP_IRQ R/W 0x0 Video configuration completed including all requested loops. This triggers once after all loops of a video complete. If both video configurations are requested to be used, it will trigger after each configuration completes.
3 VID_LOOP_COMP_IRQ R/W 0x0 Video loop completed. If multiple loops of a video are requested, this interrupt triggers after each completed loop.
2 BROWNOUT_IRQ R/W 0x0 Brownout detected
1 INIT_DONE_IRQ R/W 0x0 Initialization done
0 RESERVED R 0x0 Reserved

7.4 FPGA_VERSION Register (Address = 0x10) [reset = 0x10000000]

FPGA_VERSION is shown in FPGA_VERSION Register Field Descriptions.

Return to Summary Table.

FPGA Bitstream Version

Table 7-6 FPGA_VERSION Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-28 FPGA_BUILD_LEVEL R 0x1 FPGA bitsream build level

0x0 = Debug release, not reproducible

0x1+ = Versioned release, can be reproduced
27-20 FPGA_VERSION_MINOR R 0x0 FPGA Bitsream Minor Revision
19-12 FPGA_VERSION_MAJOR R 0x0 FPGA Bitsream Major Revision
11-0 FPGA_BUILD_NUMBER R 0x0 FPGA Bitstream build number

7.5 FMT_FLIP Register (Address = 0x20) [reset = 0x0]

FMT_FLIP is shown in FMT_FLIP Register Field Descriptions.

Return to Summary Table.

DMD Flip control register

Table 7-7 FMT_FLIP Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-5 RESERVED R 0x0 Reserved
4 FMT_CTL_DMDLFLIP R/W 0x0 DMD Long Side Flip
0x0 = no long side flip
0x1 = Enable Image flip along DMD long side
3-1 RESERVED R 0x0 Reserved
0 FMT_CTL_DMDSFLIP R/W 0x0 DMD Short Side Flip
0x0 = no short side flip
0x1 = Enable Image flip along DMD short side

7.6 RSC_SEQBUF_SELECT Register (Address = 0x44) [reset = 0x0]

RSC_SEQBUF_SELECT is shown in RSC_SEQBUF_SELECT Register Field Descriptions.

Return to Summary Table.

Sequence Buffer Select

Table 7-8 RSC_SEQBUF_SELECT Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-1 RESERVED R 0x0 Reserved
0 RSC_SEQBUF_SELECT R/W 0x0 Sequence Buffer Select

0x0 = Select sequencer buffer 0

0x1 = Select sequencer buffer 1

7.7 PWM_CONTROL Register (Address = 0x50) [reset = 0x46419064]

PWM_CONTROL is shown in PWM_CONTROL Register Field Descriptions.

Return to Summary Table.

PWM Control Register

Table 7-9 PWM_CONTROL Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31 RESERVED R 0x0 Reserved
30 PWM_EN R/W 0x1 PWM Enable
29-20 PWM_BPWM_DC R/W 0x64 Blue PWM Duty Cycle
19-10 PWM_GPWM_DC R/W 0x64 Green PWM Duty Cycle
9-0 PWM_RPWM_DC R/W 0x64 Red PWM Duty Cycle

7.8 VCM_FRAME_RATE Register (Address = 0x60) [reset = 0x00186A00]

VCM_FRAME_RATE is shown in VCM_FRAME_RATE Register Field Descriptions.

Return to Summary Table.

Frame Rate Selection

Table 7-10 VCM_FRAME_RATE Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-24 RESERVED R 0x0 Reserved
23-0 VCM_FRAME_RATE R/W 0x00186A00 Video frame time in 40-MHz clock counts.

Value should match sequence time

25 Hz = 1600000

60 Hz = 666666

7.9 VCM_START_ADDR1 Register (Address = 0x64) [reset = 0x0]

VCM_START_ADDR1 is shown in Table 7-11.

Return to Summary Table.

Video 1 start address

Table 7-11 VCM_START_ADDR1 Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-0 START_ADDR1 R/W 0x0 Video 1 start address in flash

7.10 VCM_CONFIG1 Register (Address = 0x68) [reset = 0x1001]

VCM_CONFIG1 is shown in Table 7-12.

Return to Summary Table.

Video configuration 1

Table 7-12 VCM_CONFIG1 Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-24 RESERVED R 0x0 Reserved
23-12 LOOP_CNT1 R/W 0x1 Number of times to loop video 1

0x0 = invalid

0x1 = 1 loop

0x2 = 2 loop
11-0 FRAME_CNT1 R/W 0x1 Number of frames in video 1

0x0 = invalid

0x1 = 1 frame

0x2 = 2 frames

7.11 VCM_START_ADDR2 Register (Address = 0x6C) [reset = 0x0]

VCM_START_ADDR2 is shown in Table 7-13.

Return to Summary Table.

Video 2 start address

Table 7-13 VCM_START_ADDR2 Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-0 START_ADDR2 R/W 0x0 Video 2 start address in flash

7.12 VCM_CONFIG2 Register (Address = 0x70) [reset = 0x1001]

VCM_CONFIG2 is shown in Table 7-14.

Return to Summary Table.

Video configuration 2

Table 7-14 VCM_CONFIG2 Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-24 RESERVED R 0x0 Reserved
23-12 LOOP_CNT2 R/W 0x1 Number of times to loop video 2

0x0 = invalid

0x1 = 1 loop

0x2 = 2 loop
11-0 FRAME_CNT2 R/W 0x1 Number of frames in video 2

0x0 = invalid

0x1 = 1 frame

0x2 = 2 frames

7.13 VCM_CONTROL Register (Address = 0x74) [reset = 0x10]

VCM_CONTROL is shown in Table 7-15.

Return to Summary Table.

Table 7-15 VCM_CONTROL Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-6 RESERVED R 0x0 Reserved
5 VCM_TOGGLE_CONFIGS R/W 0x0 Video buffer toggle selection

0x0 = Playback will only use the selected buffer

0x1 = Playback will use both buffers
4 VCM_LOOP_CONFIGS R/W 0x1 Loop configuration

0x1 = Repeat configuration
3 VCM_BUF_PTR R/W 0x0 Video Configuration pointer

0x0 = Play Video 1

0x1 = Play Video 2
2 VCM_AUTOSTOP R/W 0x0 Auto-stop after playback

0x0 = Repeat last frame of video playback until commanded otherwise

0x1 = Stop and park the DMD after video(s) complete
1 VCM_STOP R/W 0x0 Stop Video / Park DMD

0x0 = Allow Video Play

0x1 = Stop video playback and park DMD. Must be set to 0 to play video
0 VCM_PLAY R/W 0x0 Play video. Self-clearing

7.14 VCM_STATUS Register (Address = 0x78) [reset = 0x0]

VCM_STATUS is shown in Table 7-16.

Return to Summary Table.

Video Status Register

Table 7-16 VCM_STATUS Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-3 RESERVED R 0x0 Reserved
2 VCM_SEQABORT_ERR R 0x0 Sequence abort error Clears on video play
1 VCM_CURR_CONFIG_PTR R 0x0 Current video configuration pointer
0 VCM_VID_IN_PROGRESS R 0x0 Video in progress when set

7.15 TMP_CTRL Register (Address = 0x90) [reset = 0x00010003]

TMP_CTRL is shown in Table 7-17.

Return to Summary Table.

Temperature control register

Table 7-17 TMP_CTRL Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-17 RESERVED R 0x0 Reserved
16 TMP_CTRLEN R/W 0x1 Temperature function enable

0x0 = Disable

0x1 = Enable
15-8 TMP_I2CSLADDR R/W 0x0 TMP411 I2C slave address (for details, see TMP411 data sheet)
7-0 TMP_NFACTOR R/W 0x3 N factor to compensate TMP411 measurement (for details, see TMP411 data sheet)

7.16 TMP_STATUS Register (Address = 0x94) [reset = 0x0]

TMP_STATUS is shown in Table 7-18.

Return to Summary Table.

Temperature Status Register

Table 7-18 TMP_STATUS Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-2 RESERVED R 0x0 Reserved
1 TMP_VALID R 0x0 Temperature Status Valid

0x0 = I2C temperature read failed or not yet completed

0x1 = I2C temp read succeeded
0 TMP_PASS R 0x0 Temperature Status Pass

0x0 = Select sequencer buffer 0

0x1 = Select sequencer buffer 1

7.17 TMP_REMOTE_TEMP Register (Address = 0x98) [reset = 0x0]

TMP_REMOTE_TEMP is shown in Table 7-19.

Return to Summary Table.

DMD Temperature Measurement

Table 7-19 TMP_REMOTE_TEMP Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-28 RESERVED R 0x0 Reserved
27-16 TMP_REMOTE_FILTERED R 0x0

TMP411 Remote temperature filtered measurement

DMD temperature measurement after filtering
15-12 RESERVED R 0x0 Reserved
11-0 TMP_REMOTE_RAW R 0x0

TMP411 Remote temperature raw measurement

Single DMD temperature measurement

7.18 TMP_LOCAL_TEMP Register (Address = 0x9C) [reset = 0x0]

TMP_LOCAL_TEMP is shown in Table 7-20.

Return to Summary Table.

TMP411 Temperature Measurement

Table 7-20 TMP_LOCAL_TEMP Register Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
31-28 RESERVED R 0x0 Reserved
27-16 TMP_LOCAL_FILTERED R 0x0 TMP411 Local temperature filtered measurement

TMP411 temperature measurement after filtering
15-12 RESERVED R 0x0 Reserved
11-0 TMP_LOCAL_RAW R 0x0 TMP411 Local temperature raw measurement

Single temperature measurement