JAJSDF7A January 2017 – May 2017 LMK61E0M
PRODUCTION DATA.
The CMOSCTL register provides control over Output for LMK61E0M.
BIT NO. | FIELD | TYPE | RESET | EEPROM | DESCRIPTION | |
---|---|---|---|---|---|---|
[7:3] | RESERVED | - | - | N | Reserved. | |
[2] | OUT0_HIZ | RW | 0 | Y | Controls OUT0 in LMK61E0M. When set to 1, the output is tri-stated with high impedance. When set to 0, the output is in normal operation. | |
[1] | CMOS_MUTE | RW | 0 | Y | Output channel mute in LMK61E0M. | |
[0] | RESERVED | - | - | N | Reserved. |