Example program referenced: boostxl_afe031_f28379d_dacmode

To enable DAC mode in software, the following flow needs to be completed

• Enable DAC transmit mode internal to AFE.
  • To enable the PWM transmit mode, set the TX and PA bits in the enable register to 1, and set the DAC bit to 0.
  • Software example function: HAL_afe031_txDACEnable();
• Enable the DAC transmit mode with GPIO toggle and Configure word length for SPI
  • Set the GPIO connected the the DAC pin to 1.
  • set word length to 10 bytes for SPI communication.
  • Software example function: HAL_afe031_dacEnable();

Sending information in DAC mode, can be accomplished very similarly to how the PWM mode operates. One PWM source is used to set the DAC mode value to the correct value of the sine ramp that gets sent out. The second PWM is used for bit rate to generate an interrupt and determine what frequency needs to be outputted.

A problem does arise if attempting to reach vary precise frequencies with this implementation. The problem can be looked at with Equation 1.

If trying to generate 131.25 kHz, then only two variables can change. One approach is to set the number of steps in the sine table. For example, if there are 10 steps in the sine table the Frequency of interrupt is:

Frequency of Interrupt = (Number of Steps in Sine Table) * (Frequency of Desired Signal)

Frequency of Interrupt = 1.3125 MHz

With a 200 MHz clock,even if an interrupt occurs at either 152 or 153 CPU cycles, the interrupt frequencies would be 1.31579 MHz and 1.30719 MHz respectively. These frequencies do not fall within spec for the frequency tolerances in Table 4-1. This means setting the step size cannot be the correct implementation for precise frequency generation.

The other way to think of this is to set the frequency of interrupt. Let's set the interrupt for 1 MHz, something that is possible to generate. The number of steps in the sine wave would then be:

Number of steps in Sine Table = (1 MHz) / (131.25 kHz)

Number of Steps in sine Table = 7.61905

Utlizing the floating-point capability of the F28379D, the processor can keep track of that remainder, and now the accuracy depends on the sine table, not the 1 MHz clock. The step size can be found using the following formula:

Step Size = (Points in Sine Table)/ (Number of steps in Sine Table)

With a 4096 sine table, and continuing with the previous example, this gives 537.6 as the step size. This means in every interrupt, the sine table will step another 537.6. Since the program is sorting through an array, this number will be rounded off to 537, but as this number gets added and the program shifts through the sine table, the next step will vary off the decimal step size. An example interrupt routine is shown below:

• //Transmit next data point in sine wave. Also convert float SinePosition to unsigned int
  • Uint16 temp = sinePosition;
  • HAL_spi_xmt((sineTable[temp]) );
• //Calculate next step
  • sinePosition += sineStep; }
• //Check for overflow
  • if(sinePosition > 4095)
  • { sinePosition -= 4095; }

One aspect to note is that in this implementation, a 1 MHz Interrupt was created, which only moves data from one memory address to another. A way to make this less CPU intensive is to utilize the C2000's DMA (Direct Memory Access). The DMA peripheral moves data from one memory address to another based on a trigger event. Pre-fill two buffers with the correct data that is chosen to send out over SPI, and use the DMA to switch between the two. When switching from one buffer to the other, the older buffer will refill with the values.

In the DAC Mode software, a 1 MHz PWM signal is utilized to generate a DMA event that moves data from one of these buffers to the SPI TX Buffer. Since the older buffer needs to be re-filled after each use, the DMA will trigger an event each time it finishes reading an entire buffer. During this interrupt, the buffers are switched, and the old one is re-filled. By following this implementation, CPU utilization vs. memory tradeoffs can be weighed and the buffers can be sized accordingly. If extra memory is available, using a bigger buffer will reduce the CPU overhead. If not a lot of memory is available, then the smaller the buffer size increases the CPU overhead.

Exactly like the PWM mode software implementation, the PWM2 interrupt handles all of the FSK protocol needs. The protocol being implemented is a repeatable pattern, which allows the software to be based on a cycle count. One cycle count is the time period for one bit. In this implementation, 33 bits (11 bits per word, three words) are being sent. During each cycle, a check to see the value of the next bit and the step size changes to allow the sine table to be sent out at the mark or space frequencies. After 33 cycles, the system stops sending DAC values and enters the quiet mode. After 209 cycles, the cycle count is reset and the software starts sending the packet again.With the FSK transmission being handled by the PWM2 interrupt, the CPU's main function is free to be used for other applications. By default the software example will transmit a packet_1 referenced in Table 4-1, but this can be changed to a packet_0 by setting the packet_to_send variable to a zero.