SPRADA3 july   2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Device Nomenclature
  6. 3 R5 Cores and TCM in AM263x
    1. 3.1 R5 Core Nomenclature in Am263x
  7. 4 Example Support for AM263x Family
  8. 5 IPC Example Support for Two-Core Devices (AM2632)
    1. 5.1 Option 1 Using MulticoreImageGen.js
    2. 5.2 Option Two (Migration Guide from a Four-Core System Project to a Two-Core System Project)
  9. 6 System Project Example Support for Two-Core Devices (AM2632)
  10. 7 Target Configuration in CCS
    1. 7.1 Prerequisites
    2. 7.2 Creating a Target Configuration
  11. 8 Connecting to the Target Core
  12. 9 Hardware Description for Launch Pad and Control Card
    1. 9.1 Launchpad Pinout for Standard Analog Devices
    2. 9.2 ADC and DAC Mapping in Launchpad for Standard Analog
    3. 9.3 Pinmux Mapping - Standard Analog - Launch Pad
    4. 9.4 ADC and DAC Mapping in Control Card for Standard Analog
  13. 10Summary
  14. 11References

9.4 ADC and DAC Mapping in Control Card for Standard Analog

The AM263x Control Card has two revisions called E1 and E2. Control Cards are only built with the superset device (AM2634). Customers can scale down by purchasing select OPN devices (AM2642 or AM2631) that meet their system requirements.

The Control Card had various design changes for the E2 revision of the board. The changes are mentioned in AM263x Sitara Control Card Hardware User's Guide. The differences in ADC and DAC Mapping in Control Card for Standard Analog Devices is mentioned in Table 9-10. For the Enhanced Analog Devices, see also AM263x Sitara Control Card Hardware User's Guide.

Table 9-10 E1 Versus E2 Pin Mapping for Standard Analog Devices
HSEC E1 E2

1

NC

NC

2

NC

NC

3

TMS

TMS

4

NC

NC

5

TCK

TCK

6

TDO

TDO

7

GND

GND

8

TDI

TDI

9

DAC_OUT

ADC0_AIN0/DAC_OUT

10

GND

GND

11

ADC0_AIN0_P

ADC0_AIN1/DAC_OUT

12

ADC0_AIN0_n

ADC1_AIN0

13

GND

GND

14

ADC0_AIN1_p

ADC1_AIN1

15

ADC0_AIN1_n

ADC0_AIN2

16

GND

GND

17

ADC0_AIN2_p

ADC0_AIN3

18

ADC0_AIN2_n

ADC1_AIN2

19

GND

GND

20

ADC1_AIN0_p

ADC1_AIN3

21

ADC1_AIN0_n

ADC0_AIN4

22

GND

GND

23

ADC1_AIN1_p

ADC0_AIN5

24

ADC1_AIN1_n

ADC1_AIN4

25

ADC1_AIN2_p

NC/ADC_CAL0

26

ADC1_AIN2_n

ADC1_AIN5

27

ADC2_AIN0_p

NC/ADC_CAL1

28

ADC2_AIN0_n

NC

29

GND

GND

30

ADC2_AIN1_p

NC

31

ADC2_AIN1_n

ADC2_AIN0

32

NC

GND

33

ADC2_AIN2_p

ADC2_AIN1

34

ADC2_AIN2_n

NC

35

GND

GND

36

NC

NC

37

NC

ADC2_AIN2

38

GND

GND

39

NC

ADC2_AIN3

40

NC

NC

41

NC

NC

42

NC

NC

43

ADC_VREFLO

GND

44

NC

NC

45

ADC_VREFhi

ADC_VREFH