SWCU194 March   2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1 Target Applications
    2. 1.2 Overview
    3. 1.3 Functional Overview
      1. 1.3.1  ArmCortex-M33 with FPU
        1. 1.3.1.1 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block (SCB)
      2. 1.3.2  On-Chip Memory
        1. 1.3.2.1 SRAM
        2. 1.3.2.2 Flash Memory
        3. 1.3.2.3 ROM
      3. 1.3.3  Radio
      4. 1.3.4  Security Core
      5. 1.3.5  Runtime Security
      6. 1.3.6  General-Purpose Timers
        1. 1.3.6.1 Watchdog Timer
        2. 1.3.6.2 Always-On Domain
      7. 1.3.7  Direct Memory Access
      8. 1.3.8  System Control and Clock
      9. 1.3.9  Serial Communication Peripherals
        1. 1.3.9.1 UART
        2. 1.3.9.2 I2C
        3. 1.3.9.3 I2S
        4. 1.3.9.4 SPI
      10. 1.3.10 Programmable I/Os
      11. 1.3.11 Sensor Controller
      12. 1.3.12 Random Number Generator
      13. 1.3.13 cJTAG and JTAG
      14. 1.3.14 Power Supply System
        1. 1.3.14.1 Supply System
          1. 1.3.14.1.1 VDDS
          2. 1.3.14.1.2 VDDR
          3. 1.3.14.1.3 Digital Core Supply
          4. 1.3.14.1.4 Other Internal Supplies
        2. 1.3.14.2 DC/DC Converter
  3. 2  Arm Cortex-M33 Processor with FPU
    1. 2.1 Arm Cortex-M33 Processor Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Integrated Configurable Debug
      2. 2.3.2 Trace Port Interface Unit
      3. 2.3.3 Arm Cortex-M33 System Peripheral Details
        1. 2.3.3.1 Floating Point Unit (FPU)
        2. 2.3.3.2 Memory Protection Unit (MPU)
        3. 2.3.3.3 System Timer (SysTick)
        4. 2.3.3.4 Nested Vectored Interrupt Controller (NVIC)
        5. 2.3.3.5 System Control Block (SCB)
        6. 2.3.3.6 System Control Space (SCS)
        7. 2.3.3.7 Security Attribution Unit (SAU)
    4. 2.4 Programming Model
      1. 2.4.1 Modes of Operation and Execution
        1. 2.4.1.1 Security States
        2. 2.4.1.2 Operating Modes
        3. 2.4.1.3 Operating States
        4. 2.4.1.4 Privileged Access and Unprivileged User Access
      2. 2.4.2 Instruction Set Summary
      3. 2.4.3 Memory Model
        1. 2.4.3.1 Private Peripheral Bus
        2. 2.4.3.2 Unaligned Accesses
      4. 2.4.4 Exclusive Monitor
      5. 2.4.5 Processor Core Registers Summary
      6. 2.4.6 Exceptions
        1. 2.4.6.1 Exception Handling and Prioritization
      7. 2.4.7 Runtime Security
        1. 2.4.7.1 IDAU Watermark Registers
        2. 2.4.7.2 Secure Memory Range for Registers
        3. 2.4.7.3 Bus Topology
        4. 2.4.7.4 Intended Use
    5. 2.5 Arm® Cortex®-M33 Registers
      1. 2.5.1  CPU_ITM Registers
      2. 2.5.2  CPU_DWT Registers
      3. 2.5.3  CPU_SYSTICK Registers
      4. 2.5.4  CPU_NVIC Registers
      5. 2.5.5  CPU_SCS Registers
      6. 2.5.6  CPU_MPU Registers
      7. 2.5.7  CPU_SAU Registers
      8. 2.5.8  CPU_DCB Registers
      9. 2.5.9  CPU_SIG Registers
      10. 2.5.10 CPU_FPU Registers
      11. 2.5.11 CPU_TPIU Registers
  4. 3 Memory Map
    1. 3.1 Introduction
    2. 3.2 Memory Map (Secure and Non-secure)
      1. 3.2.1 Bus Security
    3. 3.3 Memory Map
  5. 4  Arm Cortex-M33 Peripherals
    1. 4.1 Arm Cortex-M33 Peripherals Introduction
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation and Hard Faults
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Fabric
      1. 5.4.1 Introduction
      2. 5.4.2 Event Fabric Overview
        1. 5.4.2.1 Registers
    5. 5.5 AON Event Fabric
      1. 5.5.1 Common Input Event List
      2. 5.5.2 Event Subscribers
        1. 5.5.2.1 AON Power Management Controller (AON_PMCTL)
        2. 5.5.2.2 Real-Time Clock
        3. 5.5.2.3 MCU Event Fabric
    6. 5.6 MCU Event Fabric
      1. 5.6.1 Common Input Event List
      2. 5.6.2 Event Subscribers
        1. 5.6.2.1 System CPU
        2. 5.6.2.2 NMI
        3. 5.6.2.3 Freeze
    7. 5.7 AON Events
    8. 5.8 Interrupts and Events Registers
      1. 5.8.1 AON_EVENT Registers
      2. 5.8.2 EVENT Registers
  7. 6 JTAG Interface
    1. 6.1 Overview
    2. 6.2 cJTAG
    3. 6.3 ICEPick
      1. 6.3.1 Secondary TAPs
        1. 6.3.1.1 Slave DAP (CPU DAP)
      2. 6.3.2 ICEPick Registers
        1. 6.3.2.1 IR Instructions
        2. 6.3.2.2 Data Shift Register
        3. 6.3.2.3 Instruction Register
        4. 6.3.2.4 Bypass Register
        5. 6.3.2.5 Device Identification Register
        6. 6.3.2.6 User Code Register
        7. 6.3.2.7 ICEPick Identification Register
        8. 6.3.2.8 Connect Register
      3. 6.3.3 Router Scan Chain
      4. 6.3.4 TAP Routing Registers
        1. 6.3.4.1 ICEPick Control Block
          1. 6.3.4.1.1 All0s Register
          2. 6.3.4.1.2 ICEPick Control Register
          3. 6.3.4.1.3 Linking Mode Register
        2. 6.3.4.2 Test TAP Linking Block
          1. 6.3.4.2.1 Secondary Test TAP Register
        3. 6.3.4.3 Debug TAP Linking Block
          1. 6.3.4.3.1 Secondary Debug TAP Register
    4. 6.4 ICEMelter
    5. 6.5 Serial Wire Viewer (SWV)
    6. 6.6 Halt In Boot (HIB)
    7. 6.7 Debug and Shutdown
    8. 6.8 Boundary Scan
  8. 7 Power, Reset, and Clock Management (PRCM)
    1. 7.1 Introduction
    2. 7.2 System CPU Mode
    3. 7.3 Supply System
      1. 7.3.1 Internal DC/DC Converter and Global LDO
      2. 7.3.2 External Regulator Mode
    4. 7.4 Digital Power Partitioning
      1. 7.4.1 MCU_VD
        1. 7.4.1.1 MCU_VD Power Domains
      2. 7.4.2 AON_VD
        1. 7.4.2.1 AON_VD Power Domains
    5. 7.5 Clock Management
      1. 7.5.1 System Clocks
        1. 7.5.1.1 Controlling the Oscillators
      2. 7.5.2 Clocks in MCU_VD
        1. 7.5.2.1 Clock Gating
        2. 7.5.2.2 Scaler to GPTs
        3. 7.5.2.3 Scaler to WDT
      3. 7.5.3 Clocks in AON_VD
    6. 7.6 Power Modes
      1. 7.6.1 Start-Up State
      2. 7.6.2 Active Mode
      3. 7.6.3 Idle Mode
      4. 7.6.4 Standby Mode
      5. 7.6.5 Shutdown Mode
    7. 7.7 Reset
      1. 7.7.1 System Resets
        1. 7.7.1.1 Clock Loss Detection
        2. 7.7.1.2 Software-Initiated System Reset
        3. 7.7.1.3 Warm Reset Converted to System Reset
      2. 7.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 7.7.3 Reset of AON_VD
      4. 7.7.4 Always On Watchdog Timer (AON_WDT)
    8. 7.8 PRCM Registers
      1. 7.8.1 PRCM Registers
      2. 7.8.2 AON_PMCTL Registers
      3. 7.8.3 DDI_0_OSC Registers
  9. 8 Versatile Instruction Memory System (VIMS)
    1. 8.1 Introduction
    2. 8.2 VIMS Configurations
      1. 8.2.1 VIMS Modes
        1. 8.2.1.1 GPRAM Mode
        2. 8.2.1.2 Off Mode
        3. 8.2.1.3 Cache Mode
      2. 8.2.2 VIMS FLASH Line Buffers
      3. 8.2.3 VIMS Arbitration
      4. 8.2.4 VIMS Cache TAG Prefetch
    3. 8.3 VIMS Software Remarks
      1. 8.3.1 FLASH Program or Update
      2. 8.3.2 VIMS Retention
        1. 8.3.2.1 Mode 1
        2. 8.3.2.2 Mode 2
        3. 8.3.2.3 Mode 3
    4. 8.4 FLASH
      1. 8.4.1 Flash Memory Protection
      2. 8.4.2 Flash Memory Programming
    5. 8.5 ROM Functions
    6. 8.6 VIMS Registers
      1. 8.6.1 FLASH Registers
      2. 8.6.2 VIMS Registers
      3. 8.6.3 NVMNW Registers
  10. 9 SRAM
    1. 9.1 Introduction
    2. 9.2 Main Features
    3. 9.3 Data Retention
    4. 9.4 Parity and SRAM Error Support
      1. 9.4.1 SRAM Extension Mode
    5. 9.5 SRAM Auto-Initialization
    6. 9.6 Parity Debug Behavior
    7. 9.7 SRAM Registers
      1. 9.7.1 SRAM_MMR Registers
      2. 9.7.2 SRAM Registers
  11. 10Bootloader
    1. 10.1 Bootloader Functionality
      1. 10.1.1 Bootloader Disabling
      2. 10.1.2 Bootloader Backdoor
    2. 10.2 Bootloader Interfaces
      1. 10.2.1 Packet Handling
        1. 10.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 10.2.2 Transport Layer
        1. 10.2.2.1 UART Transport
          1. 10.2.2.1.1 UART Baud Rate Automatic Detection
        2. 10.2.2.2 SPI Transport
      3. 10.2.3 Serial Bus Commands
        1. 10.2.3.1  COMMAND_PING
        2. 10.2.3.2  COMMAND_DOWNLOAD
        3. 10.2.3.3  COMMAND_GET_STATUS
        4. 10.2.3.4  COMMAND_SEND_DATA
        5. 10.2.3.5  COMMAND_RESET
        6. 10.2.3.6  COMMAND_SECTOR_ERASE
        7. 10.2.3.7  COMMAND_CRC32
        8. 10.2.3.8  COMMAND_GET_CHIP_ID
        9. 10.2.3.9  COMMAND_MEMORY_READ
        10. 10.2.3.10 COMMAND_MEMORY_WRITE
        11. 10.2.3.11 COMMAND_BANK_ERASE
        12. 10.2.3.12 COMMAND_SET_CCFG
        13. 10.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 11Device Configuration
    1. 11.1 Customer Configuration (CCFG)
      1. 11.1.1 CCFG Recommendations for Final Production
    2. 11.2 CCFG Registers
    3. 11.3 Factory Configuration (FCFG)
    4. 11.4 FCFG1 Registers
  13. 12AES and Hash Cryptoprocessor
    1. 12.1 Introduction
    2. 12.2 Functional Description
      1. 12.2.1 Debug Capabilities
      2. 12.2.2 Exception Handling
      3. 12.2.3 Power Management and Sleep Modes
      4. 12.2.4 Interrupts
      5. 12.2.5 Module Memory Map
      6. 12.2.6 Master Control and Select Module
        1. 12.2.6.1 Algorithm Select Register
          1. 12.2.6.1.1 Algorithm Select
        2. 12.2.6.2 Master PROT Enable
          1. 12.2.6.2.1 Master PROT-Privileged Access-Enable
        3. 12.2.6.3 Software Reset
      7. 12.2.7 AES Engine
        1. 12.2.7.1 Second and Third Key Registers (Internal, but Clearable)
        2. 12.2.7.2 AES Initialization Vector (IV) Registers
        3. 12.2.7.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 12.2.7.4 AES Data Input and Output Registers
        5. 12.2.7.5 TAG Registers
      8. 12.2.8 Key Area Registers
        1. 12.2.8.1 Key Store Write Area Register
        2. 12.2.8.2 Key Store Written Area Register
        3. 12.2.8.3 Key Store Size Register
        4. 12.2.8.4 Key Store Read Area Register
      9. 12.2.9 Hash Engine
        1. 12.2.9.1 Hash I/O Buffer Control and Status Register, Mode, and Length Registers
        2. 12.2.9.2 Hash Data Input and Digest Registers
    3. 12.3 DMA Controller
      1. 12.3.1 Internal Operation
      2. 12.3.2 Supported DMA Operations
    4. 12.4 AES and Hash Cryptoprocessor Performance
      1. 12.4.1 Introduction
      2. 12.4.2 Performance for DMA-Based Operations
    5. 12.5 Programming Guidelines
      1. 12.5.1 One-Time Initialization After a Reset
      2. 12.5.2 DMAC and Master Control
        1. 12.5.2.1 Regular Use
        2. 12.5.2.2 Interrupting DMA Transfers
        3. 12.5.2.3 Interrupts, Hardware, and Software Synchronization
      3. 12.5.3 Hashing
        1. 12.5.3.1 Data Format and Byte Order
        2. 12.5.3.2 Basic Hash with Data From DMA
          1. 12.5.3.2.1 New Hash Session with Digest Read Through Slave
          2. 12.5.3.2.2 New Hash Session with Digest to External Memory
          3. 12.5.3.2.3 Resumed Hash Session
        3. 12.5.3.3 HMAC
          1. 12.5.3.3.1 Secure HMAC
        4. 12.5.3.4 Alternative Basic Hash Where Data Originates from Slave Interface
          1. 12.5.3.4.1 New Hash Session
          2. 12.5.3.4.2 Resumed Hash Session
      4. 12.5.4 Encryption and Decryption
        1. 12.5.4.1 Data Format and Byte Order
        2. 12.5.4.2 Key Store
          1. 12.5.4.2.1 Load Keys from External Memory
        3. 12.5.4.3 Basic AES Modes
          1. 12.5.4.3.1 AES-ECB
          2. 12.5.4.3.2 AES-CBC
          3. 12.5.4.3.3 AES-CTR
          4. 12.5.4.3.4 Programming Sequence with DMA Data
        4. 12.5.4.4 CBC-MAC
          1. 12.5.4.4.1 Programming Sequence for Regular CBC-MAC
          2. 12.5.4.4.2 Programming Sequence for Regular CBC-MAC with Continuation
          3. 12.5.4.4.3 Programming Sequence for CMAC CBC-MAC
          4. 12.5.4.4.4 Programming Sequence for CMAC CBC-MAC with Continuation
        5. 12.5.4.5 AES-CCM
          1. 12.5.4.5.1 Continued CCM Processing
          2. 12.5.4.5.2 Programming Sequence for AES-CCM
          3. 12.5.4.5.3 Programming Sequence for Continued AES-CCM in the AAD Phase
          4. 12.5.4.5.4 Programming Sequence for Continued AES-CCM in the Payload Phase
        6. 12.5.4.6 AES-GCM
          1. 12.5.4.6.1 Continued AES-GCM Processing
          2. 12.5.4.6.2 Programming Sequence for AES-GCM
          3. 12.5.4.6.3 Programming Sequence for Continued AES-GCM in the AAD Phase
          4. 12.5.4.6.4 Programming Sequence for Continued AES-GCM in the Payload Phase
      5. 12.5.5 Exceptions Handling
        1. 12.5.5.1 Soft Reset
        2. 12.5.5.2 External Port Errors
        3. 12.5.5.3 Key Store Errors
    6. 12.6 Conventions and Compliances
      1. 12.6.1 Conventions Used in This Manual
        1. 12.6.1.1 Terminology
        2. 12.6.1.2 Formulas and Nomenclature
      2. 12.6.2 Compliance
    7. 12.7 CRYPTO Registers
  14. 13PKA Engine
    1. 13.1 Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Module Architecture
      2. 13.2.2 PKA RAM
      3. 13.2.3 PKCP Operations
      4. 13.2.4 Sequencer Operations
        1. 13.2.4.1 Modular Exponentiation Operations
        2. 13.2.4.2 Modular Inversion Operation
        3. 13.2.4.3 ECC Operations
      5. 13.2.5 Operation Sequence
    3. 13.3 PKA Engine Performance
      1. 13.3.1 Basic Operations Performance
      2. 13.3.2 ExpMod Performance
      3. 13.3.3 Modular Inversion Performance
      4. 13.3.4 ECC Operation Performance
    4. 13.4 PKA Registers
  15. 14True Random Number Generator (TRNG)
    1. 14.1 Introduction
    2. 14.2 Block Diagram
    3. 14.3 TRNG Software Reset
    4. 14.4 Interrupt Requests
    5. 14.5 TRNG Operation Description
      1. 14.5.1 TRNG Shutdown
      2. 14.5.2 TRNG Alarms
      3. 14.5.3 TRNG Entropy
    6. 14.6 TRNG Low-Level Programming Guide
      1. 14.6.1 Initialization
        1. 14.6.1.1 Interfacing Modules
        2. 14.6.1.2 TRNG Main Sequence
        3. 14.6.1.3 TRNG Operating Modes
          1. 14.6.1.3.1 Polling Mode
          2. 14.6.1.3.2 Interrupt Mode
    7. 14.7 TRNG Registers
  16. 15I/O Controller (IOC)
    1. 15.1  Introduction
    2. 15.2  IOC Overview
    3. 15.3  I/O Mapping and Configuration
      1. 15.3.1 Basic I/O Mapping
      2. 15.3.2 Mapping AUXIOs to DIO Pins
      3. 15.3.3 Control External LNA/PA (Range Extender) with I/Os
      4. 15.3.4 Map the 32 kHz System Clock (SCLK_LF Clock) to DIO
    4. 15.4  Edge Detection on DIO Pins
      1. 15.4.1 Configure DIO as GPIO Input to Generate Interrupt on Edge Detect
    5. 15.5  Unused I/O Pins
    6. 15.6  GPIO
    7. 15.7  I/O Pin Capability
    8. 15.8  Peripheral PORT_IDs
    9. 15.9  I/O Pins
      1. 15.9.1 Input/Output Modes
        1. 15.9.1.1 Physical Pin
        2. 15.9.1.2 Pin Configuration
    10. 15.10 IOC Registers
      1. 15.10.1 AON_IOC Registers
      2. 15.10.2 GPIO Registers
      3. 15.10.3 IOC Registers
  17. 16Micro Direct Memory Access (µDMA)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1  Channel Assignments
      2. 16.3.2  Priority
      3. 16.3.3  Arbitration Size
      4. 16.3.4  Request Types
        1. 16.3.4.1 Single Request
        2. 16.3.4.2 Burst Request
      5. 16.3.5  Channel Configuration
      6. 16.3.6  Transfer Modes
        1. 16.3.6.1 Stop Mode
        2. 16.3.6.2 Basic Mode
        3. 16.3.6.3 Auto Mode
        4. 16.3.6.4 Ping-Pong Mode
        5. 16.3.6.5 Memory Scatter-Gather Mode
        6. 16.3.6.6 Peripheral Scatter-Gather Mode
      7. 16.3.7  Transfer Size and Increments
      8. 16.3.8  Peripheral Interface
      9. 16.3.9  Software Request
      10. 16.3.10 Interrupts and Errors
    4. 16.4 Initialization and Configuration
      1. 16.4.1 Module Initialization
      2. 16.4.2 Configuring a Memory-to-Memory Transfer
        1. 16.4.2.1 Configure the Channel Attributes
        2. 16.4.2.2 Configure the Channel Control Structure
        3. 16.4.2.3 Start the Transfer
    5. 16.5 UDMA Registers
  18. 17Timers
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 GPTM Reset Conditions
      2. 17.3.2 Timer Modes
        1. 17.3.2.1 One-Shot or Periodic Timer Mode
        2. 17.3.2.2 Input Edge-Count Mode
        3. 17.3.2.3 Input Edge-Time Mode
        4. 17.3.2.4 PWM Mode
        5. 17.3.2.5 Wait-for-Trigger Mode
      3. 17.3.3 Synchronizing GPT Blocks
      4. 17.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 17.4 Initialization and Configuration
      1. 17.4.1 One-Shot and Periodic Timer Modes
      2. 17.4.2 Input Edge-Count Mode
      3. 17.4.3 Input Edge-Timing Mode
      4. 17.4.4 PWM Mode
      5. 17.4.5 Producing DMA Trigger Events
    5. 17.5 GPT Registers
  19. 18Real-Time Clock (RTC)
    1. 18.1 Introduction
    2. 18.2 Functional Specifications
      1. 18.2.1 Functional Overview
      2. 18.2.2 Free-Running Counter
      3. 18.2.3 Channels
        1. 18.2.3.1 Capture and Compare
      4. 18.2.4 Events
    3. 18.3 RTC Register Information
      1. 18.3.1 Register Access
      2. 18.3.2 Entering Sleep and Wakeup From Sleep
      3. 18.3.3 AON_RTC:SYNC Register
    4. 18.4 RTC Registers
      1. 18.4.1 AON_RTC Registers
  20. 19Watchdog Timer (WDT)
    1. 19.1 Introduction
    2. 19.2 Functional Description
    3. 19.3 Initialization and Configuration
    4. 19.4 WDT Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 Analog I/O Digital I/O (AIODIO)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 Semaphore (SMPH)
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPI Master (SPIM)
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 Comparator A (COMPA)
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 Comparator B (COMPB)
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference Digital-to-Analog Converter (DAC)
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 Current Source (ISRC)
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud Rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to µDMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
  24. 23Serial Peripheral Interface (SPI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
          1. 23.4.2.1.1 Repeated Transmit Operation
        2. 23.4.2.2 Receive FIFO
        3. 23.4.2.3 FIFO Flush
      3. 23.4.3 Interrupts
      4. 23.4.4 Data Format
      5. 23.4.5 Delayed Data Sampling
      6. 23.4.6 Frame Formats
        1. 23.4.6.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.6.2 Motorola SPI Frame Format
          1. 23.4.6.2.1 SPO Clock Polarity Bit
          2. 23.4.6.2.2 SPH Phase Control Bit
        3. 23.4.6.3 Motorola SPI Frame Format with SPO = 0 and SPH = 0
        4. 23.4.6.4 Motorola SPI Frame Format with SPO = 0 and SPH = 1
        5. 23.4.6.5 Motorola SPI Frame Format with SPO = 1 and SPH = 0
        6. 23.4.6.6 Motorola SPI Frame Format with SPO = 1 and SPH = 1
        7. 23.4.6.7 MICROWIRE Frame Format
    5. 23.5 μDMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SPI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format with 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization with Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command with Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond with Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          19. 26.3.3.2.19 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry from Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries from Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® Low Energy
      1. 26.6.1 Bluetooth® Low Energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® Low Energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® Low Energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Non-connectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

11.2 CCFG Registers

Table 11-1 lists the memory-mapped registers for the CCFG registers. All register offset addresses not listed in Table 11-1 should be considered as reserved locations and the register contents should not be modified.

Table 11-1 CCFG Registers
OffsetAcronymRegister NameSection
0hSIZE_AND_DIS_FLAGSCCFG Size and Disable FlagsSection 11.2.1
4hMODE_CONFMode Configuration 0Section 11.2.2
8hMODE_CONF_1Mode Configuration 1Section 11.2.3
ChVOLT_LOAD_0Voltage Load 0Section 11.2.4
10hVOLT_LOAD_1Voltage Load 1Section 11.2.5
14hEXT_LF_CLKExtern LF clock configurationSection 11.2.6
18hIEEE_MAC_0IEEE MAC Address 0Section 11.2.7
1ChIEEE_MAC_1IEEE MAC Address 1Section 11.2.8
20hIEEE_BLE_0IEEE BLE Address 0Section 11.2.9
24hIEEE_BLE_1IEEE BLE Address 1Section 11.2.10
28hBL_CONFIGBootloader ConfigurationSection 11.2.11
2ChERASE_CONFErase ConfigurationSection 11.2.12
30hERASE_CONF_1Erase Configuration 1Section 11.2.13
34hCCFG_TI_OPTIONSTI OptionsSection 11.2.14
38hCCFG_TAP_DAP_0Test Access Points Enable 0Section 11.2.15
3ChCCFG_TAP_DAP_1Test Access Points Enable 1Section 11.2.16
40hIMAGE_VALID_CONFImage ValidSection 11.2.17
44hCCFG_WEPROT_31_0_BY2KProtect Sectors 0-31Section 11.2.18
48hCCFG_WEPROT_SPARE_1Spare register for WriteErase configurationSection 11.2.19
4ChCCFG_WEPROT_SPARE_2Spare register for WriteErase configurationSection 11.2.20
50hCCFG_WEPROT_SPARE_3Spare register for WriteErase configurationSection 11.2.21
54hTRUSTZONE_FLASH_CFGTrustzone configuration register for flashSection 11.2.22
58hTRUSTZONE_SRAM_CFGTrustzone configuration register for MCU SRAMSection 11.2.23
5ChSRAM_CFGConfiguration register for MCU SRAMSection 11.2.24
64hCPU_LOCK_CFGConfiguration register for MCU CPU lock optionsSection 11.2.25
68hDEB_AUTH_CFGConfiguration register for debug authenticationSection 11.2.26
6ChCKEY0Customer keySection 11.2.27
70hCKEY1Customer keySection 11.2.28
74hCKEY2Customer keySection 11.2.29
78hCKEY3Customer keySection 11.2.30

Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for access types in this section.

Table 11-2 CCFG Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

11.2.1 SIZE_AND_DIS_FLAGS Register (Offset = 0h) [Reset = FFFFFFFFh]

SIZE_AND_DIS_FLAGS is shown in Table 11-3.

Return to the Summary Table.

CCFG Size and Disable Flags

Table 11-3 SIZE_AND_DIS_FLAGS Register Field Descriptions
Bit Field Type Reset Description
31-16 SIZE_OF_CCFG R FFFFh Total size of CCFG in bytes.
15-4 DISABLE_FLAGS R FFFh Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
3 DIS_TCXO R 1h Deprecated. Must be set to 1.
2 DIS_GPRAM R 1h Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM).
0: GPRAM is enabled and hence CACHE disabled.
1: GPRAM is disabled and instead CACHE is enabled (default).
Notes:
- Disabling CACHE will reduce CPU execution speed (up to 60%).
- GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if enabled.
See:
VIMS:CTL.MODE
1 DIS_ALT_DCDC_SETTING R 1h Disable alternate DC/DC settings.
0: Enable alternate DC/DC settings.
1: Disable alternate DC/DC settings.
See:
MODE_CONF_1.ALT_DCDC_VMIN
MODE_CONF_1.ALT_DCDC_DITHER_EN
MODE_CONF_1.ALT_DCDC_IPEAK
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field.
0 DIS_XOSC_OVR R 1h Disable XOSC override functionality.
0: Enable XOSC override functionality.
1: Disable XOSC override functionality.
See:
MODE_CONF_1.DELTA_IBIAS_INIT
MODE_CONF_1.DELTA_IBIAS_OFFSET
MODE_CONF_1.XOSC_MAX_START

11.2.2 MODE_CONF Register (Offset = 4h) [Reset = FFFFFFFFh]

MODE_CONF is shown in Table 11-4.

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Mode Configuration 0

Table 11-4 MODE_CONF Register Field Descriptions
Bit Field Type Reset Description
31-28 VDDR_TRIM_SLEEP_DELTA R Fh Signed delta value to apply to the
VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H.
0x8 (-8) : Delta = -7
...
0xF (-1) : Delta = 0
0x0 (0) : Delta = +1
...
0x7 (7) : Delta = +8
27 DCDC_RECHARGE R 1h DC/DC during recharge in powerdown.
0: Use the DC/DC during recharge in powerdown.
1: Do not use the DC/DC during recharge in powerdown (default).
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field.
26 DCDC_ACTIVE R 1h DC/DC in active mode.
0: Use the DC/DC during active mode.
1: Do not use the DC/DC during active mode (default).
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field.
25 VDDR_EXT_LOAD R 1h For TI internal use only.
24 VDDS_BOD_LEVEL R 1h VDDS BOD level.
0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum PA output power on CC13x4x10).
1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default).
23-22 SCLK_LF_OPTION R 3h Select source for SCLK_LF.
0h = 31.25 kHz clock derived from 48 MHz XOSC or HPOSC. The RTC tick speed AON_RTC:SUBSECINC is updated to 0x8637BD, corresponding to a 31.25 kHz clock (done in the SetupTrimDevice() driverlib boot function). The device must be blocked from entering Standby mode when using this clock source.
1h = External low frequency clock on DIO defined by EXT_LF_CLK.DIO. The RTC tick speed AON_RTC:SUBSECINC is updated to EXT_LF_CLK.RTC_INCREMENT (done in the SetupTrimDevice() driverlib boot function). External clock must always be running when the chip is in standby for VDDR recharge timing.
2h = 32.768 kHz low frequency XOSC
3h = Low frequency RCOSC (default)
21 VDDR_TRIM_SLEEP_TC R 1h 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated
0x0: TI's Power Manager temperature compensates VDDR_TRIM_SLEEP_DELTA every time Standby mode is entered.
When temperature compensation is performed, the delta is calculated this way:
Delta = max (delta, min(8, floor(62-temp)/8))
Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current temperature in degrees C.
20 RTC_COMP R 1h Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
19-18 XOSC_FREQ R 3h Selects which high frequency oscillator is used (required for radio usage).
0h = External 48 MHz TCXO.
Refer to MODE_CONF_1.TCXO_MAX_START and MODE_CONF_1.TCXO_TYPE bit fields for additional configuration of TCXO.
1h = Internal high precision oscillator.
2h = 48M : 48 MHz XOSC_HF
3h = 24M : 24 MHz XOSC_HF. Not supported.
17 XOSC_CAP_MOD R 1h Enable modification (delta) to XOSC cap-array. Value specified in XOSC_CAPARRAY_DELTA.
0: Apply cap-array delta
1: Do not apply cap-array delta (default)
16 HF_COMP R 1h Reserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8 XOSC_CAPARRAY_DELTA R FFh Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. Enabled by XOSC_CAP_MOD.
7-0 VDDR_CAP R FFh Unsigned 8-bit integer, representing the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF. This should take into account capacitor tolerance and voltage dependent capacitance variation. This bit affects the recharge period calculation when going into powerdown or standby.

NOTE! If using the following functions this field must be configured (used by TI RTOS):
SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown()

11.2.3 MODE_CONF_1 Register (Offset = 8h) [Reset = FFFFFFFFh]

MODE_CONF_1 is shown in Table 11-5.

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Mode Configuration 1

Table 11-5 MODE_CONF_1 Register Field Descriptions
BitFieldTypeResetDescription
31TCXO_TYPER1hSelects the TCXO type.
0: CMOS type. Internal common-mode bias will not be enabled.
1: Clipped-sine type. Internal common-mode bias will be enabled when TCXO is used.
Bit field value is only valid if MODE_CONF.XOSC_FREQ=0.
30-24TCXO_MAX_STARTR7FhMaximum TCXO startup time in units of 100us.
Bit field value is only valid if MODE_CONF.XOSC_FREQ=0.
23-20ALT_DCDC_VMINRFhMinimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
Voltage = (28 + ALT_DCDC_VMIN) / 16.
0: 1.75V
1: 1.8125V
...
14: 2.625V
15: 2.6875V
NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must be called regularly to apply this field (handled automatically if using TI RTOS!).
19ALT_DCDC_DITHER_ENR1hEnable DC/DC dithering if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0).
0: Dither disable
1: Dither enable
18-16ALT_DCDC_IPEAKR7hInductor peak current if alternate DC/DC setting is enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external inductor!
0: Min 46mA
...
4: Typical 70mA
...
7: Max 87mA
15-12DELTA_IBIAS_INITRFhSigned delta value for IBIAS_INIT. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT
11-8DELTA_IBIAS_OFFSETRFhSigned delta value for IBIAS_OFFSET. Delta value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.
See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET
7-0XOSC_MAX_STARTRFFhUnsigned value of maximum XOSC startup time (worst case) in units of 100us. Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0.

11.2.4 VOLT_LOAD_0 Register (Offset = Ch) [Reset = FFFFFFFFh]

VOLT_LOAD_0 is shown in Table 11-6.

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Voltage Load 0
Enabled by MODE_CONF.VDDR_EXT_LOAD.

Table 11-6 VOLT_LOAD_0 Register Field Descriptions
BitFieldTypeResetDescription
31-24VDDR_EXT_TP45RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
23-16VDDR_EXT_TP25RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8VDDR_EXT_TP5RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
7-0VDDR_EXT_TM15RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.

11.2.5 VOLT_LOAD_1 Register (Offset = 10h) [Reset = FFFFFFFFh]

VOLT_LOAD_1 is shown in Table 11-7.

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Voltage Load 1
Enabled by MODE_CONF.VDDR_EXT_LOAD.

Table 11-7 VOLT_LOAD_1 Register Field Descriptions
BitFieldTypeResetDescription
31-24VDDR_EXT_TP125RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
23-16VDDR_EXT_TP105RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
15-8VDDR_EXT_TP85RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.
7-0VDDR_EXT_TP65RFFhReserved for future use. Software should not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior.

11.2.6 EXT_LF_CLK Register (Offset = 14h) [Reset = FFFFFFFFh]

EXT_LF_CLK is shown in Table 11-8.

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Extern LF clock configuration

Table 11-8 EXT_LF_CLK Register Field Descriptions
BitFieldTypeResetDescription
31-24DIORFFhUnsigned integer, selecting the DIO to supply external 32 kHz clock as SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL.
23-0RTC_INCREMENTR00FFFFFFhUnsigned integer, defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: EXT_LF_CLK.RTC_INCREMENT = 238/InputClockFrequency in Hertz (e.g.: RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz)

11.2.7 IEEE_MAC_0 Register (Offset = 18h) [Reset = FFFFFFFFh]

IEEE_MAC_0 is shown in Table 11-9.

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IEEE MAC Address 0

Table 11-9 IEEE_MAC_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[31:0] of the 64-bits custom IEEE MAC address.
If different from 0xFFFFFFFF then the value of this field is applied otherwise use value from FCFG:MAC_15_4_0.

11.2.8 IEEE_MAC_1 Register (Offset = 1Ch) [Reset = FFFFFFFFh]

IEEE_MAC_1 is shown in Table 11-10.

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IEEE MAC Address 1

Table 11-10 IEEE_MAC_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[63:32] of the 64-bits custom IEEE MAC address.
If different from 0xFFFFFFFF then the value of this field is applied, otherwise use value from FCFG:MAC_15_4_1.

11.2.9 IEEE_BLE_0 Register (Offset = 20h) [Reset = FFFFFFFFh]

IEEE_BLE_0 is shown in Table 11-11.

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IEEE BLE Address 0

Table 11-11 IEEE_BLE_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[31:0] of the 64-bits custom IEEE BLE address.
If different from 0xFFFFFFFF then the value of this field is applied otherwise use value from FCFG:MAC_BLE_0.

11.2.10 IEEE_BLE_1 Register (Offset = 24h) [Reset = FFFFFFFFh]

IEEE_BLE_1 is shown in Table 11-12.

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IEEE BLE Address 1

Table 11-12 IEEE_BLE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRRFFFFFFFFhBits[63:32] of the 64-bits custom IEEE BLE address.
If different from 0xFFFFFFFF then the value of this field is applied, otherwise use value from FCFG:MAC_BLE_1.

11.2.11 BL_CONFIG Register (Offset = 28h) [Reset = C5FFFFFFh]

BL_CONFIG is shown in Table 11-13.

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Bootloader Configuration
Configures the functionality of the ROM boot loader.
If both the boot loader is enabled by the BOOTLOADER_ENABLE field and the boot loader backdoor is enabled by the BL_ENABLE field it is possible to force entry of the ROM boot loader even if a valid image is present in flash.

Table 11-13 BL_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-24BOOTLOADER_ENABLERC5hBootloader enable. Boot loader can be accessed if IMAGE_VALID_CONF.IMAGE_VALID is an invalid vector table address or BL_ENABLE is enabled (and conditions for boot loader backdoor are met).
0xC5: Boot loader is enabled.
Any other value: Boot loader is disabled.
23-17RESERVEDR0hReserved
16BL_LEVELR1hSets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field.
0: Active low.
1: Active high.
15-8BL_PIN_NUMBERRFFhDIO number that is level checked if the boot loader backdoor is enabled by the BL_ENABLE field.
7-0BL_ENABLERFFhEnables the boot loader backdoor.
0xC5: Boot loader backdoor is enabled.
Any other value: Boot loader backdoor is disabled.
NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader backdoor is enabled.

11.2.12 ERASE_CONF Register (Offset = 2Ch) [Reset = FFFFFFFFh]

ERASE_CONF is shown in Table 11-14.

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Erase Configuration

Table 11-14 ERASE_CONF Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8CHIP_ERASE_DIS_NR1hChip erase.
This bit controls if a chip erase requested through the JTAG WUC TAP will be ignored in a following boot caused by a reset of the MCU VD.
A successful chip erase operation will force the content of the flash main bank back to the state as it was when delivered by TI.
0: Disable. Any chip erase request detected during boot will be ignored.
1: Enable. Any chip erase request detected during boot will be performed by the boot FW.
7-1RESERVEDR0hReserved
0BANK_ERASE_DIS_NR1hBank erase.
This bit controls if the ROM serial boot loader will accept a received Bank Erase command (COMMAND_BANK_ERASE).
A successful Bank Erase operation will erase all main bank sectors not protected by write protect configuration bits in CCFG.
0: Disable the boot loader bank erase function.
1: Enable the boot loader bank erase function.

11.2.13 ERASE_CONF_1 Register (Offset = 30h) [Reset = FFFFFFFFh]

ERASE_CONF_1 is shown in Table 11-15.

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Erase Configuration 1

Table 11-15 ERASE_CONF_1 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0WEPROT_CCFG_NR1hWriteErase protect the CCFG sector
Setting this bit = 0 will set FLASH:WEPROT_AUX_BY1.WEPROT_B0_CCFG_BY1 = 1 during boot and hence WriteErase protect the CCFG

11.2.14 CCFG_TI_OPTIONS Register (Offset = 34h) [Reset = FFC5C5C5h]

CCFG_TI_OPTIONS is shown in Table 11-16.

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TI Options

Table 11-16 CCFG_TI_OPTIONS Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16C_FA_DISRC5hOption to disable failure analysis without customer password. If C_FA_DIS != 0xC5, CKEY (CKEY0.KEY, CKEY1.KEY, CKEY2.KEY, CKEY2.KEY) must be provided to TI for failure analysis to be possible.
0xC5: Failure analysis without customer password is enabled
All other values: Failure analysis without customer password is disabled
15-8IDAU_CFG_ENABLERC5hIDAU configuration.
0xC5: Disable IDAU configuration controlled by TRUSTZONE_FLASH_CFG and TRUSTZONE_SRAM_CFG.
All other values: Enable IDAU configuration controlled by TRUSTZONE_FLASH_CFG and TRUSTZONE_SRAM_CFG.
7-0TI_FA_ENABLERC5hTI Failure Analysis.
0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) option with the unlock code.
All other values: Disable the functionality of unlocking the TI FA option with the unlock code.

11.2.15 CCFG_TAP_DAP_0 Register (Offset = 38h) [Reset = FFC5C5C5h]

CCFG_TAP_DAP_0 is shown in Table 11-17.

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Test Access Points Enable 0

Table 11-17 CCFG_TAP_DAP_0 Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-16 CPU_DAP_ENABLE R C5h Enable CPU DAP.
0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM boot FW.
Any other value: Main CPU DAP access will remain disabled out of power-up/system-reset.
15-8 PWRPROF_TAP_ENABLE R C5h Enable PWRPROF TAP.
0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: PWRPROF TAP access will remain disabled out of power-up/system-reset.
7-0 TEST_TAP_ENABLE R C5h Enable Test TAP.
0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: TEST TAP access will remain disabled out of power-up/system-reset.

11.2.16 CCFG_TAP_DAP_1 Register (Offset = 3Ch) [Reset = FFC5C5C5h]

CCFG_TAP_DAP_1 is shown in Table 11-18.

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Test Access Points Enable 1

Table 11-18 CCFG_TAP_DAP_1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16PBIST2_TAP_ENABLERC5hEnable PBIST2 TAP.
0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: PBIST2 TAP access will remain disabled out of power-up/system-reset.
15-8PBIST1_TAP_ENABLERC5hEnable PBIST1 TAP.
0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: PBIST1 TAP access will remain disabled out of power-up/system-reset.
7-0AON_TAP_ENABLERC5hEnable AON TAP
0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI.
Any other value: AON TAP access will remain disabled out of power-up/system-reset.

11.2.17 IMAGE_VALID_CONF Register (Offset = 40h) [Reset = FFFFFFFFh]

IMAGE_VALID_CONF is shown in Table 11-19.

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Image Valid

Table 11-19 IMAGE_VALID_CONF Register Field Descriptions
BitFieldTypeResetDescription
31-0IMAGE_VALIDRFFFFFFFFhThis field must have the address value of the start of the flash vector table in order to enable the boot FW in ROM to transfer control to a flash image.
Any illegal vector table start address value will force the boot FW in ROM to transfer control to the serial boot loader in ROM.

11.2.18 CCFG_WEPROT_31_0_BY2K Register (Offset = 44h) [Reset = FFFFFFFFh]

CCFG_WEPROT_31_0_BY2K is shown in Table 11-20.

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Protect Sectors 0-31
Each bit write protects one 2KB flash sector from being both programmed and erased. Bit must be set to 0 in order to enable sector WriteErase protect.

Table 11-20 CCFG_WEPROT_31_0_BY2K Register Field Descriptions
BitFieldTypeResetDescription
31WEPROT_SEC_31_NR1h0: Sector protected
30WEPROT_SEC_30_NR1h0: Sector protected
29WEPROT_SEC_29_NR1h0: Sector protected
28WEPROT_SEC_28_NR1h0: Sector protected
27WEPROT_SEC_27_NR1h0: Sector protected
26WEPROT_SEC_26_NR1h0: Sector protected
25WEPROT_SEC_25_NR1h0: Sector protected
24WEPROT_SEC_24_NR1h0: Sector protected
23WEPROT_SEC_23_NR1h0: Sector protected
22WEPROT_SEC_22_NR1h0: Sector protected
21WEPROT_SEC_21_NR1h0: Sector protected
20WEPROT_SEC_20_NR1h0: Sector protected
19WEPROT_SEC_19_NR1h0: Sector protected
18WEPROT_SEC_18_NR1h0: Sector protected
17WEPROT_SEC_17_NR1h0: Sector protected
16WEPROT_SEC_16_NR1h0: Sector protected
15WEPROT_SEC_15_NR1h0: Sector protected
14WEPROT_SEC_14_NR1h0: Sector protected
13WEPROT_SEC_13_NR1h0: Sector protected
12WEPROT_SEC_12_NR1h0: Sector protected
11WEPROT_SEC_11_NR1h0: Sector protected
10WEPROT_SEC_10_NR1h0: Sector protected
9WEPROT_SEC_9_NR1h0: Sector protected
8WEPROT_SEC_8_NR1h0: Sector protected
7WEPROT_SEC_7_NR1h0: Sector protected
6WEPROT_SEC_6_NR1h0: Sector protected
5WEPROT_SEC_5_NR1h0: Sector protected
4WEPROT_SEC_4_NR1h0: Sector protected
3WEPROT_SEC_3_NR1h0: Sector protected
2WEPROT_SEC_2_NR1h0: Sector protected
1WEPROT_SEC_1_NR1h0: Sector protected
0WEPROT_SEC_0_NR1h0: Sector protected

11.2.19 CCFG_WEPROT_SPARE_1 Register (Offset = 48h) [Reset = FFFFFFFFh]

CCFG_WEPROT_SPARE_1 is shown in Table 11-21.

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Spare register for WriteErase configuration

Table 11-21 CCFG_WEPROT_SPARE_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDRFFFFFFFFhReserved

11.2.20 CCFG_WEPROT_SPARE_2 Register (Offset = 4Ch) [Reset = FFFFFFFFh]

CCFG_WEPROT_SPARE_2 is shown in Table 11-22.

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Spare register for WriteErase configuration

Table 11-22 CCFG_WEPROT_SPARE_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDRFFFFFFFFhReserved

11.2.21 CCFG_WEPROT_SPARE_3 Register (Offset = 50h) [Reset = FFFFFFFFh]

CCFG_WEPROT_SPARE_3 is shown in Table 11-23.

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Spare register for WriteErase configuration

Table 11-23 CCFG_WEPROT_SPARE_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDRFFFFFFFFhReserved

11.2.22 TRUSTZONE_FLASH_CFG Register (Offset = 54h) [Reset = FFFFFFFFh]

TRUSTZONE_FLASH_CFG is shown in Table 11-24.

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Trustzone configuration register for flash

Table 11-24 TRUSTZONE_FLASH_CFG Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16-10NSADDR_BOUNDARYR7FhValue will be written to PRCM:NVMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5.
9-0NSCADDR_BOUNDARYR3FFhValue will be written to PRCM:NVMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5.

11.2.23 TRUSTZONE_SRAM_CFG Register (Offset = 58h) [Reset = FFFFFFFFh]

TRUSTZONE_SRAM_CFG is shown in Table 11-25.

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Trustzone configuration register for MCU SRAM

Table 11-25 TRUSTZONE_SRAM_CFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-9NSADDR_BOUNDARYR1FFhValue will be written to PRCM:SRAMNSADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5.
8-0NSCADDR_BOUNDARYR1FFhValue will be written to PRCM:SRAMNSCADDR.BOUNDARY by ROM boot FW only if CCFG_TI_OPTIONS.IDAU_CFG_ENABLE != 0xC5.

11.2.24 SRAM_CFG Register (Offset = 5Ch) [Reset = FFFFFFFFh]

SRAM_CFG is shown in Table 11-26.

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Configuration register for MCU SRAM

Table 11-26 SRAM_CFG Register Field Descriptions
BitFieldTypeResetDescription
31-8MEM_SELR00FFFFFFhValue will be written to SRAM_MMR:MEM_CTL.MEM_SEL by ROM boot FW
7-1RESERVEDR0hReserved
0PARITY_DISR1hValue will be inverted and then written to PRCM:MCUSRAMCFG.PARITY_EN by ROM boot FW

11.2.25 CPU_LOCK_CFG Register (Offset = 64h) [Reset = FFFFFFFFh]

CPU_LOCK_CFG is shown in Table 11-27.

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Configuration register for MCU CPU lock options

Table 11-27 CPU_LOCK_CFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4LOCKNSVTOR_NR1hValue will be inverted and written to PRCM:CPULOCK.LOCKNSVTOR by ROM boot FW
3LOCKSVTAIRCR_NR1hValue will be inverted and written to PRCM:CPULOCK.LOCKSVTAIRCR by ROM boot FW
2LOCKSAU_NR1hValue will be inverted and written to PRCM:CPULOCK.LOCKSAU by ROM boot FW
1LOCKNSMPU_NR1hValue will be inverted and written to PRCM:CPULOCK.LOCKNSMPU by ROM boot FW
0LOCKSMPU_NR1hValue will be inverted and written to PRCM:CPULOCK.LOCKSMPU by ROM boot FW

11.2.26 DEB_AUTH_CFG Register (Offset = 68h) [Reset = FFFFFFFFh]

DEB_AUTH_CFG is shown in Table 11-28.

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Configuration register for debug authentication

Table 11-28 DEB_AUTH_CFG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3INTSPNIDENR1hValue will be written to CPU_DCB:DAUTHCTRL.INTSPNIDEN by ROM boot FW
2SPNIDENSELR1hValue will be written to CPU_DCB:DAUTHCTRL.SPNIDENSEL by ROM boot FW
1INTSPIDENR1hValue will be written to CPU_DCB:DAUTHCTRL.INTSPIDEN by ROM boot FW
0SPIDENSELR1hValue will be written to CPU_DCB:DAUTHCTRL.SPIDENSEL by ROM boot FW

11.2.27 CKEY0 Register (Offset = 6Ch) [Reset = 0FFFFFFFh]

CKEY0 is shown in Table 11-29.

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Customer key

Table 11-29 CKEY0 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR0FFFFFFFhBit[31:0] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5.

11.2.28 CKEY1 Register (Offset = 70h) [Reset = 0FFFFFFFh]

CKEY1 is shown in Table 11-30.

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Customer key

Table 11-30 CKEY1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR0FFFFFFFhBit[63:32] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5.

11.2.29 CKEY2 Register (Offset = 74h) [Reset = 0FFFFFFFh]

CKEY2 is shown in Table 11-31.

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Customer key

Table 11-31 CKEY2 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR0FFFFFFFhBit[95:64] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5.

11.2.30 CKEY3 Register (Offset = 78h) [Reset = 0FFFFFFFh]

CKEY3 is shown in Table 11-32.

Return to the Summary Table.

Customer key

Table 11-32 CKEY3 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR0FFFFFFFhBit[127:96] of customer key used for XOR of TI unlock code when CCFG_TI_OPTIONS.C_FA_DIS != 0xC5.