SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The SPI can generate interrupts when the following conditions are observed:
TX FIFO service (with the TX FIFO level configured via SPI:IFLS.TXIFLSEL)
RX FIFO service (with the RX FIFO level configured via SPI:IFLS.RXIFLSEL)
RX FIFO timeout
RX FIFO overrun
TX FIFO empty
TX DMA done/RX DMA done
Idle
Parity error
All interrupt events are ORed together before sent to the event fabric, so the SPI generates a single interrupt request regardless of the number of active interrupts. The interrupt conditions listed above can be masked by setting the appropriate bit in the SPI:IMASK register. Setting the appropriate mask bit in the SPI:IMASK register enables the interrupt.
The status of the individual interrupt sources can be read from the SPI Raw Interrupt Status register (SPI:RIS) and the SPI Masked Interrupt Status register (SPI:MIS) (see Section 23.7 for details).
The transmit FIFO service interrupt request SPI:RIS.TX is not gated with the SPI enable signal, which allows data to be written to the transmit FIFO by an interrupt service routine (ISR), before enabling the SPI.
The receive FIFO overflow interrupt SPI:RIS.RXFIFO_OVF is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the receive shift register, but not in the FIFO.
The parity error interrupt SPI:RIS.PER is set when a parity error is detected. SPI:CTL1.PEN bit can be written to enable the parity check, where the last bit received will be used as parity to test the integrity of the previous bits. SPI:CTL1.PES bit selects the parity mode as even or odd. When a parity fault is detected, the interrupt flag SPI:RIS.PER is set (to mark the data as invalid).
The idle interrupt SPI:RIS.IDLE is set when the SPI transmission has concluded and SPI module is back to idle mode. This is set when SPI:STAT.BUSY goes low.
The SPI slave Receive Timeout interrupt is set when SPI is in Slave mode and has not been receiving data for the number of functional clock cycles of the SPI clock (PERDMACLK) configured by SPI:CTL1.RXTIMEOUT. A value of 0 disables this function. The countdown is started when SPI is in the slave mode and the first CLK positive edge is detected and is countdown is restarted on each subsequent CLK positive edge. A timeout error is asserted if the count reaches zero before the next CLK toggles.