SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The SPI peripheral provides an interface to the μDMA controller with separate channels for transmit and receive. The SPI DMA Control register (SPI:DMACR) allows the μDMA to operate together with the SPI. When μDMA operation is enabled, the SPI asserts a μDMA request on the receive or transmit channel when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted whenever any data is in the RX FIFO. Whenever data in the RX FIFO reaches the configured level set via SPI:IFLS.RXIFLSEL, a burst transfer request is asserted. For the transmit channel, a single transfer request is asserted whenever at least one empty location is in the TX FIFO. Whenever the TX FIFO reaches the configured level set via SPI:IFLS.TXIFLSEL, the burst request is asserted. The μDMA controller handles the single and burst μDMA transfer requests automatically depending on how the μDMA channel is configured.
To enable μDMA operation for the receive channel, set the SPI:DMACR.RXDMAE register bit. To enable μDMA operation for the transmit channel, set the SPI:DMACR.TXDMAE register bit. If the μDMA is enabled and appropriate bits are cleared in the DMA Done Mask register (UDMA:DONEMASK) the μDMA controller triggers an interrupt when a transfer completes. The interrupt occurs on the SPI interrupt vector. If interrupts are used for SPI operation and the μDMA is enabled, the SPI interrupt handler must be designed to handle the μDMA completion interrupt. The status of TX and RX DMA done interrupts can be read from the Channel Request Done register (UDMA:REQDONE). They can also be read from SPI:RIS.DMA_DONE_TX and SPI:RIS.DMA_DONE_RX register bits. These can be used for generating an interrupt as well. For clearing the TX and RX DMA done interrupts, the corresponding bits in the UDMA:REQDONE register must be 1.
For more details about programming the μDMA controller, see Chapter 423.