SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 20-270 lists the memory-mapped registers for the AUX_SCE registers. All register offset addresses not listed in Table 20-270 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CTL | Internal | Section 20.8.12.1 |
4h | FETCHSTAT | Internal | Section 20.8.12.2 |
8h | CPUSTAT | Internal | Section 20.8.12.3 |
Ch | WUSTAT | Internal | Section 20.8.12.4 |
10h | REG1_0 | Internal | Section 20.8.12.5 |
14h | REG3_2 | Internal | Section 20.8.12.6 |
18h | REG5_4 | Internal | Section 20.8.12.7 |
1Ch | REG7_6 | Internal | Section 20.8.12.8 |
20h | LOOPADDR | Internal | Section 20.8.12.9 |
24h | LOOPCNT | Internal | Section 20.8.12.10 |
28h | NONSECDDIACC0 | Non-Secure DDI Access 0 | Section 20.8.12.11 |
2Ch | NONSECDDIACC1 | Non-Secure DDI Access 1 | Section 20.8.12.12 |
30h | NONSECDDIACC2 | Non-Secure DDI Access 2 | Section 20.8.12.13 |
34h | NONSECDDIACC3 | Non-Secure DDI Access 3 | Section 20.8.12.14 |
Complex bit access types are encoded to fit into small table cells. Table 20-271 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CTL is shown in Table 20-272.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | FORCE_EV_LOW | R/W | 0h | Internal. Only to be used through TI provided API. |
23-16 | FORCE_EV_HIGH | R/W | 0h | Internal. Only to be used through TI provided API. |
15-8 | RESET_VECTOR | R/W | 0h | Internal. Only to be used through TI provided API. |
7 | RESERVED | R | 0h | Reserved |
6 | DBG_FREEZE_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
5 | FORCE_WU_LOW | R/W | 0h | Internal. Only to be used through TI provided API. |
4 | FORCE_WU_HIGH | R/W | 0h | Internal. Only to be used through TI provided API. |
3 | RESTART | R/W | 0h | Internal. Only to be used through TI provided API. |
2 | SINGLE_STEP | R/W | 0h | Internal. Only to be used through TI provided API. |
1 | SUSPEND | R/W | 0h | Internal. Only to be used through TI provided API. |
0 | CLK_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
FETCHSTAT is shown in Table 20-273.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | OPCODE | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | PC | R | 0h | Internal. Only to be used through TI provided API. |
CPUSTAT is shown in Table 20-274.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | BUS_ERROR | R | 0h | Internal. Only to be used through TI provided API. |
10 | SLEEP | R | 0h | Internal. Only to be used through TI provided API. |
9 | WEV | R | 0h | Internal. Only to be used through TI provided API. |
8 | HALTED | R | 0h | Internal. Only to be used through TI provided API. |
7-4 | RESERVED | R | 0h | Reserved |
3 | V_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
2 | C_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
1 | N_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
0 | Z_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
WUSTAT is shown in Table 20-275.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | EXC_VECTOR | R | 0h | Internal. Only to be used through TI provided API. |
15-9 | RESERVED | R | 0h | Reserved |
8 | WU_SIGNAL | R | 0h | Internal. Only to be used through TI provided API. |
7-0 | EV_SIGNALS | R | 0h | Internal. Only to be used through TI provided API. |
REG1_0 is shown in Table 20-276.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG1 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG0 | R | 0h | Internal. Only to be used through TI provided API. |
REG3_2 is shown in Table 20-277.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG3 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG2 | R | 0h | Internal. Only to be used through TI provided API. |
REG5_4 is shown in Table 20-278.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG5 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG4 | R | 0h | Internal. Only to be used through TI provided API. |
REG7_6 is shown in Table 20-279.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG7 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG6 | R | 0h | Internal. Only to be used through TI provided API. |
LOOPADDR is shown in Table 20-280.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | STOP | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | START | R | 0h | Internal. Only to be used through TI provided API. |
LOOPCNT is shown in Table 20-281.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | ITER_LEFT | R | 0h | Internal. Only to be used through TI provided API. |
NONSECDDIACC0 is shown in Table 20-282.
Return to the Summary Table.
Non-Secure DDI Access 0
When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.
If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.
Examples:
Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | Reserved |
22 | RD_EN | R/W | 0h | Read Enable 0: AUX_SCE is not allowed to read DDI half-word given by ADDR. 1: AUX_SCE is allowed to read DDI half-word given by ADDR. |
21-16 | ADDR | R/W | 0h | Address AUX_SCE is allowed to update this DDI half-word using SET or CLR access. |
15-0 | WR_MASK | R/W | 0h | Mask AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask. |
NONSECDDIACC1 is shown in Table 20-283.
Return to the Summary Table.
Non-Secure DDI Access 1
When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.
If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.
Examples:
Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | Reserved |
22 | RD_EN | R/W | 0h | Read Enable 0: AUX_SCE is not allowed to read DDI half-word given by ADDR. 1: AUX_SCE is allowed to read DDI half-word given by ADDR. |
21-16 | ADDR | R/W | 0h | Address AUX_SCE is allowed to update this DDI half-word using SET or CLR access. |
15-0 | WR_MASK | R/W | 0h | Mask AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask. |
NONSECDDIACC2 is shown in Table 20-284.
Return to the Summary Table.
Non-Secure DDI Access 2
When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.
If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.
Examples:
Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | Reserved |
22 | RD_EN | R/W | 0h | Read Enable 0: AUX_SCE is not allowed to read DDI half-word given by ADDR. 1: AUX_SCE is allowed to read DDI half-word given by ADDR. |
21-16 | ADDR | R/W | 0h | Address AUX_SCE is allowed to update this DDI half-word using SET or CLR access. |
15-0 | WR_MASK | R/W | 0h | Mask AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask. |
NONSECDDIACC3 is shown in Table 20-285.
Return to the Summary Table.
Non-Secure DDI Access 3
When system is in secure state, AUX_SCE is allowed to update a predefined DDI half-word using SET or CLR access. Configuration will determine if AUX_SCE can read the same half-word. An access to a non-allowed register will suspend the AUX_SCE when system state is secure.
If ADDR field in two or more NONSECDDIACC registers are equal, the MASK and RD_EN from the highest numbered register will be used.
Examples:
Half-word with address of 0 corresponds to DDI_0_OSC:CTL0 bit range [15:0].
Half-word with address of 1 corresponds to DDI_0_OSC:CTL0 bit range [31:16].
…
Half-word with address of 34 corresponds to DDI_0_OSC:STAT2 bit range [15:0].
Half-word with address of 35 corresponds to DDI_0_OSC:STAT2 bit range [31:16].
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | Reserved |
22 | RD_EN | R/W | 0h | Read Enable 0: AUX_SCE is not allowed to read DDI half-word given by ADDR. 1: AUX_SCE is allowed to read DDI half-word given by ADDR. |
21-16 | ADDR | R/W | 0h | Address AUX_SCE is allowed to update this DDI half-word using SET or CLR access. |
15-0 | WR_MASK | R/W | 0h | Mask AUX_SCE is allowed to update bits in half-word given by ADDR according to this bit mask. |